Dynamic Dejitter Buffer Allocation for Variable Network Traffic
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Solution Overview
Problem
Existing dejitter buffer management in network communication systems is inefficient due to static memory allocation, leading to wasteful use of expensive FPGA memory and inability to dynamically adjust to varying traffic flow rates, which affects memory utilization and scalability.
Innovation Solution
Implement a shared central memory pool with a controller and arbiter to dynamically allocate dejitter buffer memory based on traffic flow rates, allowing flexible and efficient use of memory resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If static memory allocation is used for dejitter buffers in FPGA, then memory allocation is simple and stable, but memory utilization efficiency deteriorates due to inability to adapt to varying traffic flow rates
Solution Approach 1:
The patent implements dynamic memory allocation for dejitter buffers, where the memory size allocated to each buffer can be adjusted at runtime based on the actual traffic flow rate requirements. This allows the system to adapt to varying traffic conditions without requiring FPGA reconfiguration, resolving the contradiction between adaptability and device complexity by making the memory allocation flexible rather than fixed.
Solution Approach 2:
The system changes the memory allocation parameters dynamically based on traffic flow characteristics. By monitoring traffic flow rates and adjusting the memory size allocated to each dejitter buffer accordingly, the system achieves adaptability to different traffic conditions while maintaining manageable complexity through parameter adjustment rather than structural changes.
2Loss of energy
If static memory allocation is used for all traffic flows, then memory management is simplified, but memory resource efficiency deteriorates due to uniform allocation regardless of traffic rate
Solution Approach 1:
The patent applies local quality by allocating memory resources differently to different dejitter buffers based on their specific traffic flow rate requirements. Instead of uniform allocation, each buffer receives the appropriate memory size needed for its traffic characteristics, reducing overall memory waste while maintaining simple management through a centralized allocation mechanism.
Solution Approach 2:
The system dynamically adjusts the memory allocation parameters for each dejitter buffer based on traffic flow rates. This allows the system to optimize memory resource utilization by allocating more memory to high-rate traffic flows and less to low-rate flows, thereby reducing memory waste while keeping the allocation process manageable through automated parameter adjustment.
3Adaptability or versatility
If FPGA image change is required for memory reconfiguration, then memory allocation is fixed and stable, but system flexibility deteriorates due to inability to perform run-time configuration
Solution Approach 1:
The patent implements dynamic memory allocation that can be adjusted at runtime without requiring FPGA reconfiguration. The system uses a memory management unit that can reallocate memory from the central pool to individual dejitter buffers on-the-fly, enabling run-time configuration capability while avoiding the time-consuming process of loading new FPGA images.
Solution Approach 2:
The patent introduces a memory management unit as an intermediary between the central memory pool and dejitter buffers. This intermediary component handles run-time memory allocation and reconfiguration requests, allowing the system to adapt to changing traffic conditions without requiring direct FPGA reconfiguration, thereby eliminating reconfiguration time while maintaining stability.
4Productivity
If larger memory is allocated to accommodate high-rate traffic flows, then high-rate traffic can be handled, but memory cost increases due to expensive FPGA internal memory
Solution Approach 1:
The patent merges multiple dejitter buffers into a single shared central memory pool, where memory resources are consolidated and allocated dynamically to individual buffers based on their traffic flow rate requirements. This approach allows the system to handle high-rate traffic flows when needed while minimizing overall memory consumption by sharing resources across multiple buffers rather than allocating dedicated memory to each.
Solution Approach 2:
The system dynamically adjusts the memory allocation parameters for each dejitter buffer based on traffic flow rates. When a buffer needs to handle high-rate traffic, its allocated memory increases accordingly; when traffic rate decreases, the allocated memory decreases. This dynamic parameter adjustment enables the system to maintain handling capacity for high-rate traffic while minimizing memory resource consumption during normal operation.
Data Source
AI summary
Techniques for management of a dejitter buffer for network communication. A system includes ports to receive emulated traffic transmitted over a packet network, a central memory pool, a controller to allocate memory from the central memory pool dejitter buffers, and an arbiter to arbitrate read and write access from the ports to the central memory pool for the of dejitter buffers. A portion of the central memory pool is allocated as a respective dejitter buffer for each of the plurality of ports, based on a transmission rate associated with each respective port. The controller is capable of allocating any portion of the central memory pool as the dejitter buffer for any respective port, and the controller is configured to, during operation, dynamically change the portion of the central memory pool allocated as the dejitter buffer for a given port.