Delay-Adaptive Clock-Gated Flip-Flop Units Without Clock Glitches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing design of edge-triggered flip-flops in standard cell libraries of EDA tools does not effectively reduce dynamic power consumption, which is a significant concern in digital circuit design.
Innovation Solution
A design method for a flip-flop unit that selects a clock gating circuit based on the delay condition of a clock control signal, coupling it with an edge-triggered flip-flop to generate a second clock signal that disables clock flipping and data transmission during invalid clock control signal states, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a traditional edge-triggered flip-flop is used without clock gating, then the circuit maintains simple structure and high speed, but dynamic power consumption is high due to continuous clock flipping
Solution Approach 1:
The patent applies clock gating technology to dynamically control the clock signal to the flip-flop based on whether data transmission is needed. The clock gating circuit selectively enables or disables the clock signal, making the system adaptive to actual operational requirements and reducing unnecessary clock transitions that cause dynamic power consumption.
Solution Approach 2:
The patent changes the clock signal parameter (enabled/disabled state) based on data transmission requirements. By controlling the clock gating circuit to modify the clock signal's active state, the system reduces dynamic power consumption while maintaining functional requirements through parameter modulation rather than structural overhaul.
2Loss of energy
If clock gating circuit is added to reduce dynamic power consumption, then power consumption decreases, but the number of logic devices and layout area increase
Solution Approach 1:
The patent extracts the essential function of clock control from the main flip-flop structure and implements it through a separate clock gating circuit. By taking out the clock enabling function and implementing it independently, the design achieves power reduction while maintaining a modular structure that can be efficiently laid out, minimizing the area penalty.
3Adaptability or versatility
If multiple types of clock gating circuits are designed to handle different delay conditions, then adaptability to different delay requirements improves, but device complexity increases
Solution Approach 1:
The patent segments the clock gating circuit design into multiple types (first, second, and third clock gating circuits) each optimized for specific delay conditions. By dividing the overall clock gating function into specialized segments, the system achieves high adaptability to different delay requirements while keeping each individual circuit type relatively simple and manageable.
Data Source
AI summary
Disclosed is a flip-flop unit design method comprising: analyzing signal delay of a clock control signal in a digital circuit; selecting a clock gating circuit among a plurality of types of clock gating circuits according to the signal delay, and coupling at least one edge-triggered flip-flop and the selected clock gating circuit to be a flip-flop unit, wherein the plurality of types of clock gating circuits enable or disable a first clock signal according to the clock control signal to generate a second clock signal, and the edge-triggered flip-flop transmits data at an edge of the second clock signal. The design method eliminates the glitch in the clock signal generated by the clock gating circuit, reduces the number of logic devices of the clock gating circuit, reduces the power consumption of the clock gating circuit. The design method is applicable to a flip-flop group with any number of edge-triggered flip-flops.