Delay-Domain ADC LUT Calibration for Nonlinearity Correction
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Solution Overview
Problem
Existing delay domain analog-to-digital converters (ADCs) suffer from systematic non-linearity due to mismatches between the calibration path and the signal path, which are not adequately corrected by current calibration methods, especially in high data rate applications.
Innovation Solution
A self-referenced background calibration loop is implemented using two half ADCs (HADCs) to estimate and correct systematic integral non-linearity by computing differences in their outputs, adjusting the contents of look-up table (LUT) memories to account for mismatches, and applying corrections for second harmonic distortion due to flicker noise across multiple Nyquist bands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If delay domain ADC is used for high data rate applications, then data conversion performance is improved, but systematic non-linearity errors increase due to mismatches between calibration path and signal path
Solution Approach 1:
The patent implements a feedback mechanism where the difference between calibration path output and signal path output is continuously measured and used to adjust the LUT correction values. This closed-loop feedback eliminates systematic non-linearity errors by dynamically compensating for path mismatches, thereby maintaining high linearity accuracy while operating at high data conversion rates.
Solution Approach 2:
The patent changes the parameters stored in the LUT memory based on measured differences between calibration and signal paths. By dynamically adjusting the correction values in the LUT, the system compensates for systematic non-linearity errors, improving measurement precision without reducing the data conversion rate.
2Measurement precision
If calibration corrections are applied to compensate for path mismatches, then linearity is improved, but device complexity increases due to additional calibration circuitry and processing
Solution Approach 1:
The patent makes the ADC system multi-functional by enabling it to perform both normal signal conversion and self-calibration using the same hardware resources. The same ADC circuitry is used for both signal path processing and calibration path processing, eliminating the need for separate dedicated calibration hardware and reducing overall device complexity.
Solution Approach 2:
The patent implements a self-service calibration mechanism where the ADC system automatically performs its own calibration without requiring external calibration equipment or complex external control systems. The system uses its own output as the calibration source and automatically computes and applies correction values, simplifying the overall device architecture.
3Measurement precision
If look-up table memory is used to correct non-linearity, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies partial correction by using the LUT to compensate only for systematic non-linearity errors rather than attempting to correct all possible sources of distortion. This selective correction approach maintains adequate conversion accuracy while minimizing the computational complexity and power consumption associated with LUT operations.
Solution Approach 2:
The patent dynamically updates the LUT parameters only when necessary based on measured path mismatches, rather than continuously rewriting the entire LUT. This parameter change strategy maintains conversion accuracy by applying corrections only when systematic errors are detected, thereby reducing the power consumption of memory access and processing operations.
Data Source
AI summary
A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.