Delay-Domain ADC Threshold Calibration for Residue Stage Linearity
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Solution Overview
Problem
Pipelined analog-to-digital converters (ADCs) are limited in operating speed, making them unsuitable for high-speed applications like RF-sampling receivers, and delay-domain ADCs with non-linear delay profiles require complex calibration techniques to achieve linearity.
Innovation Solution
A delay-domain ADC architecture with independently calibratable null delay thresholds in residue stages, utilizing trim circuits and select logic to adjust delay residues, allowing asynchronous operation and reducing the need for look-up tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If delay-domain ADC architecture is used to achieve high operating speed, then operating speed is improved, but non-linearity in delay profile increases
Solution Approach 1:
The TDC is divided into multiple residue stages, each handling a portion of the delay residue. This segmentation allows independent calibration of each stage's null delay threshold, enabling correction of the exponential non-linearity while maintaining high operating speed.
Solution Approach 2:
The patent introduces trim circuits that can adjust the null delay threshold parameter in each residue stage. By changing this parameter through calibration, the exponential delay profile is linearized, resolving the non-linearity issue while preserving the high-speed advantage of delay-domain ADC.
2Manufacturing precision
If look-up tables are used to linearize delay profile, then linearity is improved, but device complexity increases
Solution Approach 1:
The patent performs calibration in advance by adjusting trim circuits during a calibration phase before normal operation. The null delay thresholds are pre-adjusted to linearize the delay profile, eliminating the need for complex look-up tables during actual conversion operations.
Solution Approach 2:
The patent replaces the software-based look-up table linearization method with a hardware-based trim circuit adjustment mechanism. This substitution simplifies the overall system by using direct electrical adjustment of delay thresholds rather than complex digital correction algorithms.
3Manufacturing precision
If multiple trim circuits are added for independent calibration, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies trim circuits selectively in specific residue stages where calibration is most beneficial. Each trim circuit is localized to adjust the null delay threshold in its specific stage, providing precise local control without requiring complex global calibration mechanisms.
Data Source
AI summary
An analog-to-digital converter including a voltage-to-delay circuit, a plurality of residue stages coupled in a sequence, and select logic. A first residue stage generates a bit output and a residue delay signal, a second residue stage generates a bit output and a residue delay signal responsive to the residue delay signal from the first residue stage, and a third residue stage generates a bit output and a residue delay signal responsive to the residue delay signal from the second residue stage. The third residue stage includes a plurality of trim circuits, the selection of which is controlled by the bit output of two or more preceding residue stages in the sequence.