Variable-Capacitance Delay Adjustor for Sub-Picosecond Timing Control

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Solution Overview

Problem

Current delay adjustors in integrated circuits offer only about 10 ps adjustable resolution for propagation delay time, which is insufficient for high-speed circuits and special applications where higher resolution is needed to maintain normal operation under process, voltage, and temperature variations.

Innovation Solution

A delay adjustor comprising a capacitance unit and a variable capacitance unit connected in series, where the capacitance of the variable unit is adjusted by control signals to enhance resolution, utilizing multiple capacitors and switches to achieve finer adjustments in propagation delay time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the capacitor-paralleling method is used to adjust propagation delay time, then the delay adjustment capability is achieved, but the adjustable resolution is limited to about 10 ps

Engineering Contradiction:
Improveadjustable resolution of propagation delay timeVSAvoidcomplexity of capacitance adjustment structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The capacitance unit is divided into multiple sub-capacitances (first sub-capacitance, second sub-capacitance, third sub-capacitance, etc.) that are connected in parallel. Each sub-capacitance can be independently controlled by its own control signal, enabling fine-grained adjustment of the total capacitance value. This segmentation allows the delay adjustor to achieve 0.1 ps resolution by selectively activating individual sub-capacitances rather than adjusting a single large capacitor.

Inventive Principle:
Principle #1Segmentation

2Reliability

If process, voltage, and temperature variations occur, then the propagation delay time becomes unpredictable, but increasing delay adjustment resolution requires more complex circuit structures

Engineering Contradiction:
Improvepredictability of propagation delay time under PVT variationsVSAvoidcomplexity of delay compensation structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The delay adjustor employs multiple variable capacitances that can be dynamically adjusted through control signals in response to process, voltage, and temperature variations. Each sub-capacitance is controlled independently, allowing the system to adaptively compensate for PVT variations by modifying the total capacitance value. This dynamic adjustment capability ensures predictable propagation delay time under varying operating conditions without requiring an overly complex fixed-structure compensation circuit.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution increases the resolution of delay time adjustment to 0.1 ps, allowing for precise control of signal propagation and improving circuit characteristics in high-speed applications by effectively compensating for variations in process, voltage, and temperature.

Implementation Method 1

a variable capacitance unit that is coupled in series to the first capacitance unit wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS7692459B2High resolution delay adjustor
Publication Date: 2010.04.06 REALTEK SEMICON CORP
  • US7692459B2 patent drawing
  • US7692459B2 patent drawing
  • US7692459B2 patent drawing

AI summary

A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.