Delay Analysis Module for DUV Verification Timing
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Solution Overview
Problem
Calculating and identifying delays in input data packets within complex Design or System Under Verification (DUV/SUV) is time-consuming and cumbersome without a standalone module, especially as complexity increases, making it difficult to diagnose deviations from expected delays.
Innovation Solution
A system and method that maintains timing information for input data packets by assigning a unique identifier and determining delay identifiers and modes, using a testbench with a prediction unit and data integrity checker to compare expected and actual packets, populating data fields, and generating reports on delay statistics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual calculation and identification of delays in input data packets is performed without a standalone module, then device complexity is reduced, but productivity decreases due to time-consuming and cumbersome delay analysis
Solution Approach 1:
A standalone delay analysis module is introduced as an intermediary component between the DUV/SUV and the verification environment. This module automatically captures timing information, assigns unique identifiers to data packets, determines delay identifiers and modes, and generates delay statistics reports, thereby resolving the contradiction by improving productivity through automation while managing complexity through modular design
Solution Approach 2:
The delay analysis module operates autonomously within the verification system, self-managing the entire delay analysis process including packet tracking, timing measurement, and report generation without requiring external manual intervention, thus improving productivity while containing complexity within a self-contained unit
2Loss of time
If complex DUV/SUV designs are verified without automated delay tracking, then device complexity is minimized, but loss of time increases due to difficulty in diagnosing delay deviations
Solution Approach 1:
The delay analysis module performs preliminary actions by maintaining timing information and assigning unique identifiers to data packets as they enter the DUV/SUV, preparing all necessary data structures and tracking mechanisms in advance, which enables rapid delay diagnosis without manual intervention when deviations occur
Solution Approach 2:
The module implements continuous feedback by comparing expected delays with actual measured delays, automatically identifying deviations and generating diagnostic reports that provide real-time information about delay issues, thereby reducing diagnosis time while managing complexity through systematic feedback mechanisms
Data Source
AI summary
Disclosed is a system for providing an inference associated with delays in processing input data packet(s) by a Design Under Verification (DUV)/System Under Verification (SUV) characterized by maintaining timing information of the input data packet(s) is disclosed. To provide an inference, initially, an input data packet is processed by a DUV or SUV. Simultaneously, an expected data packet corresponding to the input data packet is predicted and a Unique Identifier is assigned to the expected data packet corresponding to the input data packet that entered into the DUV/SUV. After assigning the Unique Identifier, the plurality of data fields pertaining to the Unique Identifier are populated in an array of Packet Timing Entries based on a Delay Identifier (ID) and a Delay Mode. The plurality of data fields may then be used for reporting various delay statistics and operational behaviour of DUV/SUV.