Delay Budget Allocation via Timing Path Trimming
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Solution Overview
Problem
Existing methodologies for delay budget assignment in integrated circuit design are computationally expensive and prone to inaccuracies, especially as circuit complexity increases, due to the need to evaluate multiple paths and approximate scaling factors.
Innovation Solution
The method involves defining timing edges and determining delay budget allocations based on (S,T) pairs associated with timing paths, trimming non-significant paths to reduce complexity, and calculating scaling factors for forward and backward paths to determine accurate delay budget allocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all paths through a component are evaluated to determine the smallest scaling factor, then timing accuracy is improved, but computational expense increases significantly
Solution Approach 1:
The patent extracts only the critical paths that actually determine the scaling factor, eliminating unnecessary path evaluations. By identifying and processing only the essential paths (those that could potentially be critical based on preliminary timing analysis), the system achieves accurate scaling factor determination without evaluating every possible path, thus resolving the contradiction between timing accuracy and computational efficiency
Solution Approach 2:
The patent performs preliminary timing analysis to identify candidate critical paths before performing the full scaling factor calculation. This preliminary action filters out non-critical paths in advance, allowing the system to focus computational resources only on paths that will actually determine the scaling factor, thereby maintaining accuracy while reducing overall computational expense
2Productivity
If an approximation method is used to compute scaling factors, then computational expense is reduced, but timing accuracy deteriorates
Solution Approach 1:
The patent applies different levels of analysis to different paths based on their criticality. Instead of uniformly treating all paths the same, the system identifies locally critical paths (those with tight timing constraints) and applies detailed evaluation only to those, while using simpler methods for non-critical paths. This localized quality approach maintains high accuracy where needed while improving overall computational efficiency
Solution Approach 2:
The patent segments the path evaluation process into multiple stages: preliminary filtering to identify candidate critical paths, and detailed analysis only for those candidates. This segmentation allows the system to use computationally expensive exact methods only where necessary (for critical paths) while using cheaper approximation methods for the majority of non-critical paths, thus resolving the contradiction between efficiency and accuracy
Data Source
AI summary
Systems and methods for determining delay budget allocations for circuit elements. One embodiment comprises a method including defining timing edges and corresponding timing paths in an integrated circuit design, and determining delay budget allocations for each of the edges based on required arrival time and design slack (S,T) pairs associated with the different timing paths. The required arrival time is a maximum time when associated with forward paths, and a minimum time when associated with backward paths. (S,T) pairs associated with some timing paths are discarded (i.e., the corresponding timing paths are trimmed) to reduce the complexity of the delay budget allocation computations. Remaining (S,T) pairs are used to determine scaling factors for significant timing paths through the edges. The smallest of the scaling factors for each edge can be multiplied by an initial delay associated with the edge to produce a delay budget allocation associated with the edge.