Selectable Delay Buffer Segmentation for Ultra-Low-Voltage Timing
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Solution Overview
Problem
Existing circuit designs for ultra-low voltage applications face challenges in efficiently tuning delay paths across multiple voltage and frequency ranges, leading to potential hold time violations and suboptimal performance in IoT and automotive products.
Innovation Solution
The implementation of a selectable delay buffer with a combination of fixed and adjustable delay sections, utilizing PMOS and NMOS pass gates and multiplexers, allows for dynamic tuning of delay paths based on operating voltage levels, ensuring correct circuit operation and optimizing timing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed delay buffer is used in ultra-low voltage designs, then the circuit structure is simple, but the delay path cannot be tuned for different voltage levels leading to hold time violations
Solution Approach 1:
The delay buffer transitions from a fixed structure to a dynamic structure where the delay amount can be adjusted based on operating conditions. Multiple delay segments are introduced that can be selectively activated through control signals, allowing the buffer to adapt its delay characteristics to different voltage levels and frequency ranges, thereby preventing hold time violations while maintaining structural manageability.
Solution Approach 2:
The delay buffer is divided into multiple discrete delay segments, each optimized for specific voltage ranges. This segmentation allows selective activation of appropriate delay segments based on the operating voltage level, providing fine-grained control over the total delay amount and enabling compliance with hold time requirements across varying operating conditions.
2Productivity
If delay segments are selectively activated based on voltage levels, then timing characteristics are optimized, but control circuit complexity increases
Solution Approach 1:
The delay buffer incorporates voltage detection functionality that automatically senses the operating voltage level and autonomously selects the appropriate delay segment without requiring external control logic. This self-service mechanism simplifies the overall control circuit complexity while still achieving optimized timing characteristics for the current operating conditions.
Solution Approach 2:
The control circuit incorporates feedback mechanisms that monitor the operating voltage and frequency conditions, then adjust the active delay segment accordingly. This feedback-based control ensures that the delay path is continuously optimized for the current operating point, maximizing the maximum clock frequency while keeping the control logic manageable through systematic feedback loops.
3Adaptability or versatility
If delay paths are not tuned for different voltage levels, then the design is simpler, but over-design for maximum delay or under-design for minimum delay occurs
Solution Approach 1:
The delay buffer exploits changes in propagation delay parameters of logic elements with voltage to its advantage. By introducing multiple delay segments with different delay characteristics and selectively activating them based on voltage level, the system adapts to different operating conditions without requiring complete redesign. This parameter-based adaptation enables the same physical hardware to serve multiple voltage ranges efficiently.
Data Source
AI summary
Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.