Delay Calibration Circuit for Matching Open-Loop Chain Timing
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Solution Overview
Problem
The characteristics of an open-loop delay chain vary with temperature, voltage, and processing, leading to inconsistencies in delay time, which are not accurately replicated by a delay-locked loop, necessitating a method to optimize the delay time duplication across chains.
Innovation Solution
A delay calibration circuit and method that adjusts the current ratio of a second delay chain by comparing the delay times of the last two stages of the second chain with the first delay chain of a delay-locked loop, using flip-flops and adjustment circuits to fine-tune the current ratios to match the delay times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the delay time of the open-loop delay chain is used directly, then the pulse-width control capability is improved, but the delay time varies with temperature, voltage, and processing leading to inconsistencies
Solution Approach 1:
The patent implements a feedback mechanism by comparing the delay time of the open-loop delay chain with that of the delay-locked loop using XOR gates and flip-flops. The comparison result feeds back to adjust the current ratio, thereby compensating for variations in delay time caused by temperature, voltage, and processing differences, and ensuring consistent delay characteristics.
Solution Approach 2:
The patent changes the current ratio parameter dynamically to compensate for delay time variations. By adjusting the current ratio based on the comparison between the open-loop delay chain and the delay-locked loop, the system maintains consistent delay characteristics across different operating conditions without requiring physical reconfiguration.
2Reliability
If the delay time of the delay-locked loop is copied to the open-loop delay chain, then the delay consistency is improved, but the complexity of the calibration circuit increases
Solution Approach 1:
The patent uses the delay-locked loop as a reference model and copies its delay time characteristics to the open-loop delay chain. By using XOR gates to compare the two delay chains and flip-flops to capture the comparison result, the system replicates the stable delay properties of the delay-locked loop in the open-loop configuration, achieving consistent delay times across different operating conditions.
3Measurement precision
If the basic frequency of the system is increased, then the pulse-width adjustment precision is improved, but the system's basic frequency limitation prevents further fine-tuning
Solution Approach 1:
The patent introduces a new dimension of control by using delay time adjustment instead of relying solely on frequency increase. By controlling the delay time of the open-loop delay chain through current ratio adjustment, the system achieves fine pulse-width control without needing to increase the basic frequency, thereby overcoming the frequency limitation while maintaining high precision.
Data Source
AI summary
A delay calibration circuit includes a first delay chain, a second delay chain, and a calibration circuit. The first delay chain includes a plurality of first delay units and delays a clock signal with a first delay to generate a first delay signal. The supply current for each of the first delay units is a first current. The second delay chain includes a plurality of second delay units and a third delay unit. The second delay units delay a first signal with a second delay to generate a second delay signal. The third delay unit delays the second delay signal to generate the third delay signal. The supply current for each unit in the second delay chain is a second current. The calibration circuit adjusts a current ratio of the second current to the first current based on the second delay signal and the third delay signal.