Clock Timing Monitor Circuit With Delay-Cell Glitch Detection
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Solution Overview
Problem
Existing electronic devices face challenges in securely managing clock signals, which are critical for synchronization and security, as they are vulnerable to tampering and variations in clock characteristics.
Innovation Solution
A clock monitor circuit is introduced, comprising a delay line of delay cells with comparator portions, which compares aspects of the monitored clock signal to expected values and outputs a failure detection signal, along with a glitch detection circuit to identify narrow glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a clock monitor circuit with delay line and comparator portions is implemented, then detection precision of clock signal deviations is improved, but device complexity increases
Solution Approach 1:
The clock monitor circuit is segmented into multiple delay cells (first delay cell, second delay cell, etc.), each with its own comparator portion. Each delay cell processes a specific time window of the clock signal independently, allowing precise detection of clock characteristics at different phases while distributing the overall complexity across modular units rather than requiring a single complex circuit.
2Reliability
If multiple delay cells with comparator portions are used to monitor clock signals, then reliability of clock signal detection is improved, but use of energy increases
Solution Approach 1:
The delay cells are configured to monitor only specific critical time windows and phases of the clock signal rather than continuously analyzing the entire clock period. The first delay cell monitors the first time window and the second delay cell monitors the second time window, focusing computational resources on the most critical detection points to maintain reliability while reducing overall energy consumption compared to continuous full-period monitoring.
3Measurement precision
If delay line with multiple delay cells is implemented, then measurement precision of clock characteristics is improved, but device complexity increases
Solution Approach 1:
The delay line is segmented into discrete delay cells connected in series, where each delay cell introduces a controlled time delay. This segmentation allows the circuit to sample the clock signal at multiple precise time points (first time window, second time window, etc.) without requiring a single complex high-precision delay mechanism, thereby achieving high measurement precision through modular simplicity.
4Measurement precision
If clock monitor circuit compares clock signal to expected values at multiple points, then detection precision is improved, but loss of time increases
Solution Approach 1:
The delay cells are configured to sample and compare the clock signal at periodic intervals corresponding to specific phases of the clock cycle. The first delay cell operates on the first time window and the second delay cell operates on the second time window in a periodic manner synchronized with the clock signal, enabling precise detection across multiple points without requiring continuous processing that would increase time loss.
Data Source
AI summary
A clock monitor circuit detects departures from expected values for clock period, clock high time duration, or clock low time duration. A delay line of the clock monitor circuit is composed of delay portions of delay cells. Each delay cell also has a comparator portion with logic to compare aspects of the monitored clock signal to corresponding expected values, and to output a failure detection signal indicating whether the expected values are met. Expected values may be read from a fuse set. The delay of the delay line may be programmatically adjusted. The clock monitor circuit may be combined with a circuit that detects narrow glitches in the monitored clock signal. Devices and systems with one or more monitored clock signals, and methods of clock signal monitoring, are also described.