Delay Cell Decoding for Linear DLL Timing and Balanced Loading
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Solution Overview
Problem
Existing delay locked loop (DLL) circuits in synchronous electronic systems face challenges in achieving linear delay timing performance, leading to unbalanced loading and nonlinear delays when incrementing delay periods.
Innovation Solution
A delay apparatus and method that utilize a series of delay cells and decoding units to generate sub control signals, ensuring only one delay cell is active at a time, allowing for precise and linear delay adjustments by successively connecting delay units with distinct delay periods, thereby maintaining balanced loading across the delay elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple delay cells are activated simultaneously to achieve larger delay periods, then the delay range is improved, but unbalanced loading occurs causing nonlinear delay timing performance
Solution Approach 1:
The delay apparatus is segmented into multiple delay cells (first delay cell, second delay cell, third delay cell) that can be independently controlled. Each delay cell has its own enable signal, allowing selective activation. This segmentation prevents unbalanced loading by ensuring only one delay cell is active at a time, maintaining linear delay timing performance while achieving extended delay range through sequential activation.
2Loss of time
If delay cells are connected in parallel to increase delay range, then the delay amount is improved, but loading becomes unbalanced leading to nonlinear delays
Solution Approach 1:
The delay cells are dynamically controlled through enable signals that activate only one delay cell at a time. The system transitions between different delay cell configurations dynamically, selecting which delay cell to activate based on the required delay period. This dynamic control maintains balanced loading conditions while achieving variable delay amounts, preventing nonlinear delays.
3Device complexity
If a single delay cell is used to maintain simple structure, then device complexity is reduced, but the delay range and flexibility are limited
Solution Approach 1:
Multiple delay cells are designed with identical structures and functions, each capable of providing a specific delay period. The enable signals allow any of the delay cells to be activated based on requirements, making the system universally adaptable to different delay needs. This multi-functionality approach maintains structural simplicity through repetition while significantly expanding the delay range and flexibility.
Data Source
AI summary
The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of delay cells for respectively delaying the input signal by a certain delay period; and a sub decoding unit for generating a plurality of sub control signals to each of the delay units according to a first control signal and a selecting signal, wherein only delay cell of all the delay units is outputted at a time according to the sub controls signals.