Delay-Cell Logic Controller for Glitch Filtering With Fewer Flip-Flops

The invention segments the glitch filtering function into multiple stages using a series of delay cells (first delay cell, second delay cell, third delay cell, fourth delay cell) connected in sequence. Each delay cell introduces a specific time delay, and by comparing signals at different delay stages using counters and comparators, the system can identify and filter glitch signals without requiring a large number of flip-flops. This segmentation approach distributes the filtering function across multiple simple components rather than using many complex flip-flops.

The invention introduces delay cells as intermediary components between the input signal and the filtering logic. These delay cells act as mediators that create time-separated versions of the input signal, allowing the counter and comparator circuits to detect glitches by comparing signals at different time points. This intermediary approach enables effective glitch filtering while using fewer active filtering components (flip-flops).

The filtering function is segmented into multiple delay stages with simple delay cells rather than using many power-consuming flip-flops. Each delay cell consumes minimal power, and the segmented approach allows the system to achieve the same filtering effect with significantly lower total power consumption.

The invention uses simple, low-power delay cells that can be easily replaced or reset rather than complex flip-flops. The delay cells are designed to be simple temporal delay elements that consume minimal power, effectively replacing the need for multiple power-hungry flip-flops while maintaining glitch filtering capability.