Current-Starved Delay Cell for Glitch-Free Low-Voltage Timing
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Solution Overview
Problem
Semiconductor delay cells consume excessive power during signal transitions due to short-through currents and glitches at high impedance nodes, which can collapse a chip or cause malfunctions, especially in low power supply systems.
Innovation Solution
A glitch-free delay cell circuit with current starved stages and decoupling capacitors is implemented, using PMOS and NMOS transistors to control the rise/fall time of signals and discharge unwanted charge, minimizing transition current through a current over capacitor approach and Power-on-Reset signal initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional delay cells are used to control signal transitions, then delay functionality is achieved, but excessive transition current is consumed due to short-through currents and glitches
Solution Approach 1:
The delay cell is divided into multiple current-starved stages, where each stage processes the signal sequentially. This segmentation allows the total transition current to be distributed across multiple smaller current pulses rather than one large simultaneous current, reducing peak current consumption while maintaining the required delay function
Solution Approach 2:
Decoupling capacitors are introduced as intermediary elements between circuit nodes to absorb and discharge unwanted charge accumulations. These capacitors act as local energy reservoirs that smooth out current variations and prevent glitch propagation, thereby reducing transition current while maintaining signal integrity
2Use of energy by moving object
If current starved stages are used to minimize transition current, then power consumption is reduced, but the circuit complexity increases
Solution Approach 1:
Multiple functional elements are merged into unified circuit blocks: current-starving transistors are integrated directly into the delay stages, decoupling capacitors are placed at critical nodes within the delay cell structure, and control logic is combined with the delay functionality. This merging reduces overall circuit complexity while maintaining power savings
Solution Approach 2:
The delay cell circuit is designed to perform multiple functions simultaneously: it provides signal delay, minimizes transition current through current-starving, suppresses glitches via decoupling capacitors, and controls rise/fall times. This multi-functionality reduces the need for separate dedicated circuits, thereby managing complexity while achieving power reduction
3Reliability
If decoupling capacitors are added to discharge unwanted charge, then glitches are eliminated, but the device complexity increases
Solution Approach 1:
Decoupling capacitors are strategically placed only at specific high-impedance nodes within the delay cell where charge accumulation and glitch generation are most problematic. This localized approach ensures glitch-free operation at critical points without adding capacitors throughout the entire circuit, thereby managing device complexity while achieving reliable glitch-free operation
Data Source
AI summary
An integrated circuit delay cell includes an input circuit to establish a current level in the circuit, a switch configured to control an on/off time of a delay circuit, a delay circuit including at least one current starved stage configured to mirror the current level, the delay circuit configured to control a speed of a rise and/or fall time of an output signal, and a glitch discharging circuit connected to the delay circuit configured to tolerate and discharge unwanted charge of the delay circuit.