Delay-Cell VCO Current Partitioning for Low-Noise Wideband PLLs
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Solution Overview
Problem
Voltage-controlled oscillators with CMOS ring oscillator configurations face challenges in maintaining phase noise and jitter characteristics, particularly when operating at low frequencies, due to reduced drive capability of buffer inverters and higher latch inverter holding capability, making them unsuitable for wideband PLL applications.
Innovation Solution
The implementation of a voltage-controlled oscillator with cascade-connected delay cells, where each delay cell includes both buffer and latch inverters, and separate current sources from voltage-current conversion circuits for each, ensuring adequate drive capability across a wide frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a CMOS ring oscillator configuration is used, then the oscillator achieves a compact area and wide frequency range, but the phase noise and jitter characteristics deteriorate at low frequencies
Solution Approach 1:
The oscillator is divided into multiple delay cells (first delay cell, second delay cell, third delay cell) that are cascade-connected. Each delay cell contains buffer inverters and latch inverters that are separately controlled by different current sources, allowing independent optimization of drive capability and phase noise characteristics across different frequency ranges
Solution Approach 2:
Different portions of the circuit (buffer inverters vs. latch inverters) are provided with different current sources from voltage-current conversion circuits. This allows each portion to have optimized current characteristics tailored to its specific function, with buffer inverters receiving current optimized for drive capability and latch inverters receiving current optimized for holding capability and phase noise performance
2Speed
If the current supplied to buffer inverters is reduced for low frequency operation, then the oscillation frequency decreases, but the drive capability of buffer inverters decreases making them unsuitable for wideband PLL applications
Solution Approach 1:
The oscillator uses multiple voltage-current conversion circuits that can dynamically adjust the current supplied to different delay cells based on the operating frequency range. This allows the drive capability to be maintained at low frequencies by providing adequate current from the voltage-current conversion circuits, while enabling wide frequency operation through dynamic current adjustment
Solution Approach 2:
The current supply is segmented into multiple independent voltage-current conversion circuits, each controlling specific delay cells. This segmentation allows different current levels to be provided to different parts of the oscillator simultaneously, maintaining drive capability in buffer inverters while enabling low frequency operation through reduced current in latch inverters
Data Source
AI summary
A voltage-controlled oscillator includes a delay circuit. The delay circuit includes a first buffer inverter which receives one of the differential input signal and outputs an other of the differential output signal, a second buffer inverter which receives the other of the differential input signal and outputs the one of the differential output signal, a first latch inverter which receives the one of the differential output signal, and includes an output connected to an output of the first buffer inverter, and a second latch inverter which receives the other of the differential output signal, and includes an output connected to an output of the second buffer inverter. The first latch inverter and the first buffer inverter receive a current produced from different voltage-current conversion circuits.