Delay Chain CDAC Control With Fewer Lines and Smaller Area

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Solution Overview

Problem

Existing delay chains in semiconductor integrated circuits face challenges in reducing area footprint while maintaining efficient control over propagation delays due to the large number of control lines required for capacitor digital-to-analog converters (CDACs).

Innovation Solution

Implementing a delay chain with separately adjustable capacitor digital-to-analog converters (SA_CDACs) and a controller using a digital thermometer encoding scheme to reduce the number of control lines, allowing for monotonic delay tuning and area reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If traditional CDACs with multiple control lines are used in delay chains, then propagation delay control is achieved, but area footprint increases due to large number of control lines

Engineering Contradiction:

Improvepropagation delay controlVSAvoidarea footprint

Core Design Contradiction:

Ease of operationVSArea of stationary object

Solution Approach 1:

Multiple control lines are merged into a single control line by encoding the control signals. The delay chain uses a compressed control scheme where multiple capacitance control signals are combined into one control line that can selectively adjust the capacitive load at different delay stages, reducing the number of control lines from multiple per stage to a single shared control line.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The single control line serves multiple functions by being able to control different capacitance values at different delay stages. The control signal on this universal control line can selectively adjust the capacitive load at any or all delay stages, making one control line perform the work of multiple dedicated control lines.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Measurement precision

If more control lines are used for precise delay tuning, then delay adjustment precision is improved, but device complexity increases

Engineering Contradiction:

Improvedelay adjustment precisionVSAvoidcontrol line complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The control approach changes from multiple discrete control lines to a single control line with encoded parameters. The control signal contains information about which capacitance to adjust and by how much, encoding multiple control parameters into a single signal that can be decoded at each delay stage to achieve precise delay tuning.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The physical control line structure is replaced with a logical control scheme. Instead of having physical separate control lines for each capacitance adjustment, the system uses a single physical control line with logically encoded commands that are decoded at each stage, substituting physical complexity with logical organization.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250260398A1Delay chain and method of operating same

Publication Date: 2025.08.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A delay chain includes: delay stages coupled in series, each delay stage including a driver device coupled between an input node and an output node of the delay stage, and a capacitor digital-to-analog converter (CDAC) coupled to the output node of the delay stage; at least one of the CDACs being a separately adjustable (SA) type of CDAC (SA_CDAC) that is separately adjustable relative to at least another one of the CDACs; and a controller configured to adjust the at least one CDAC.