Self-Calibrating Delay Chain for Uniform Delay Cells

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Solution Overview

Problem

Existing delay chains in circuits like delay-lock loops and time-to-digital converters face challenges due to manufacturing and material variances, leading to mismatched delays between cells, which current statistical calibration methods cannot accurately address without significant overhead in circuit area and power consumption.

Innovation Solution

A self-calibrating delay chain with a calibration circuit that uses a time amplifier to amplify and digitize time differences between delay cells, allowing for precise measurement and adjustment of delays to ensure uniformity, employing a multiplexer, time amplifier, and time-to-digital converter to generate digital outputs for controlling delay cell settings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If statistical calibration methods are used to calibrate delay cells, then delay uniformity is improved, but circuit area and power consumption increase significantly

Engineering Contradiction:
Improvedelay uniformityVSAvoidpower consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The delay cell calibration circuit uses self-service by having the delay cells automatically calibrate themselves through feedback from the time amplifier and time-to-digital converter, eliminating the need for external statistical calibration methods and reducing power consumption overhead

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The calibration system implements feedback by measuring the actual delay of each delay cell using the time amplifier and TDC, comparing it to the target delay, and adjusting the delay cell parameters accordingly to achieve uniform delay across all cells

Inventive Principle:
Principle #23Feedback

2Measurement precision

If high-resolution time-to-digital converters are used for calibration, then measurement precision is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improvedelay measurement precisionVSAvoidconverter complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The time amplifier amplifies the time difference dimension before digitization, allowing a lower-resolution TDC to achieve the same effective measurement precision that would otherwise require a high-resolution TDC, thereby reducing device complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The time amplifier acts as an intermediary between the delay cell output and the TDC, amplifying the time difference signal so that the TDC can accurately measure small delay variations without requiring inherently high resolution

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables accurate and efficient calibration of delay cells, reducing the need for high-resolution time-to-digital converters and minimizing power consumption while ensuring uniform delay intervals, thus improving the precision and reliability of multi-phased clocking signals.

Implementation Method 1

selectively amplifying a time difference between an output signal and an input signal of the variable delay cell to generate an amplified time difference

Methodology Applied
Scientific EffectTime amplification:

Implementation Method 2

digitalizing the amplified time difference into a digital delay value

Methodology Applied
Scientific EffectTime-to-digital conversion:

Data Source

PatentUS8219343B2Method and apparatus for calibrating a delay chain
Publication Date: 2012.07.10 REALTEK SEMICON CORP
  • US8219343B2 patent drawing
  • US8219343B2 patent drawing
  • US8219343B2 patent drawing

AI summary

Apparatus and methods are provided for calibration within a delay chain. In various embodiments, such apparatus and techniques can be used to address delay mismatch, but are not limited to such applications. Additional apparatus, systems, and methods are disclosed.