Delay-Chain Clock Jitter Measurement Without Probe Perturbation
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Solution Overview
Problem
Existing methods for measuring clock jitter in circuit devices are inaccurate due to the introduction of perturbations by external test probes and on-chip test structures, leading to uncertainty in clock frequency and increased area and power consumption, while also making it difficult to determine the effectiveness of design changes on jitter reduction.
Innovation Solution
A method and circuit device that includes a delay chain with a hierarchical multiplexer and logic circuit to iteratively determine the location of the clock signal edge within the delay chain, allowing for precise adjustment of sampling points to accurately measure clock jitter without external calibration or analog components, thereby reducing uncertainty and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If external test probes are used to measure clock jitter, then measurement capability is provided, but measurement precision deteriorates due to signal perturbation
Solution Approach 1:
The measurement function is extracted from external test probes and integrated directly into the circuit device through on-chip test structures. This eliminates the harmful interaction between external probes and the clock signal, removing the source of measurement error while preserving measurement capability.
Solution Approach 2:
A delay chain composed of multiple delay elements is introduced as an intermediary structure between the clock signal and measurement points. This delay chain provides controlled propagation paths that allow accurate sampling of clock edges without directly perturbing the original clock signal, enabling precise jitter measurement.
2Measurement precision
If a large number of flip-flops are used in on-chip test structures to accurately sample the clock signal, then measurement precision improves, but area consumption increases
Solution Approach 1:
The test structure uses a dynamic scanning mechanism where flip-flops are sequentially configured to sample different points along the delay chain through control signals. This allows a limited number of flip-flops to effectively monitor multiple clock edges over time, achieving high measurement precision without requiring a proportional increase in hardware resources.
Solution Approach 2:
The same set of flip-flops serves multiple functions: they act as both the clock signal sampling elements and the storage elements for the delay chain. This multi-functionality reduces the total number of components needed, thereby reducing area consumption while maintaining measurement precision.
3Device complexity
If each delay element has a fixed delay time, then device complexity is reduced, but measurement precision deteriorates due to quantization error
Solution Approach 1:
The delay chain is segmented into multiple discrete delay elements, each contributing a small, fixed delay portion. By dividing the total delay path into many small segments, the quantization error for each individual element is minimized, allowing precise determination of clock edge locations through the cumulative effect of many fine-grained delay stages.
Data Source
AI summary
In an embodiment, a method is disclosed that includes receiving a clock signal at a delay chain of a circuit device and determining a value of the clock signal at a selected point within the delay chain. The method also includes adjusting the selected point when the value does not indicate detection of an edge of the clock signal.