Delay-Chain Clock Generator for Seamless External Clock Loss
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Solution Overview
Problem
Electronic devices face challenges in generating a clock signal internally without consuming excessive silicon area and incurring additional costs for trimming circuitry, while switching to an internal oscillator often results in time delays due to the need for settling times in circuits like PLLs and DLLs.
Innovation Solution
A clock generation circuit utilizing a delay chain with programmable delay cells and a multiplexer to alternately receive and output delayed reference clock signals and last clock signals, allowing seamless transition to an internal clock signal generation, reducing overhead and silicon area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an internal oscillator is used to generate clock signals during periods when external clock signals are not supplied, then the electronic device can operate independently, but the silicon area consumption increases and trimming circuitry is required
Solution Approach 1:
The delay chain circuit is designed to perform multiple functions: it can operate as an external clock signal receiver during normal operation, and simultaneously function as an internal clock signal generator when external signals are unavailable. This multi-functionality eliminates the need for separate internal oscillator circuitry, reducing silicon area while maintaining clock signal availability
Solution Approach 2:
The circuit uses its own delay chain infrastructure to generate internal clock signals without requiring additional dedicated internal oscillator components. The existing delay cells and multiplexers are repurposed to serve dual roles, making the system self-sufficient during external clock unavailability without increasing overall circuit complexity
2Adaptability or versatility
If the electronic device switches to using an internal oscillator, then it can operate without external clock signals, but time delay occurs due to settling time requirements of PLLs and DLLs
Solution Approach 1:
A multiplexer serves as an intermediary component that seamlessly switches between external clock signals and internally generated clock signals. This intermediary mechanism allows for smooth transitions without the settling time delays associated with traditional PLL/DLL-based switching, as the multiplexer can rapidly switch clock sources without requiring phase or frequency synchronization
Solution Approach 2:
The circuit maintains readiness for internal clock generation by keeping the delay chain infrastructure in a standby state that can immediately activate internal clock signal generation when external signals become unavailable, eliminating the need for preliminary settling time that would otherwise be required by PLLs and DLLs
3Reliability
If traditional internal oscillator circuitry is implemented, then independent clock generation is achieved, but overhead circuitry is required to manage transition time delays
Solution Approach 1:
The circuit merges the external clock reception function and internal clock generation function into a single integrated delay chain structure. By combining these previously separate functions into one unified circuit block, the patent eliminates the need for separate overhead circuitry to manage transitions between clock sources, as the same infrastructure handles both operations
Data Source
AI summary
A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.