Delay Chain Component Interval Determination

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Solution Overview

Problem

Existing input/output circuits using delay chains face uncertainty in delay per stage, making it difficult to design the correct chain length, particularly in new technologies, leading to potential non-working interface circuits.

Innovation Solution

A system and method that iteratively adjusts the number of components in a delay chain to determine the delay time interval by activating components until the output signal transitions from low to high logic value, calculating the interval based on these transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a delay chain with a selected number of components is used to delay a clock signal, then the delay time interval can be adjusted, but the delay per stage is not known precisely making it difficult to design the correct chain length

Engineering Contradiction:
Improvedelay time interval measurementVSAvoiddelay chain design complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system performs preliminary measurement of the actual delay per stage by iteratively activating components and detecting output signal logic values before finalizing the delay chain design. This preliminary characterization allows accurate determination of delay parameters without requiring complex theoretical calculations during the design phase.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from the output signal logic value detection to iteratively adjust the number of activated components. The circuit monitors whether the output signal has a high or low logic value and uses this information to determine the correct chain length, creating a closed-loop measurement system that automatically characterizes the delay chain.

Inventive Principle:
Principle #23Feedback

2Reliability

If too short of a chain is utilized, then the design is simpler, but it leads to non-working interface circuit

Engineering Contradiction:
Improveinterface circuit functionalityVSAvoiddelay chain length determination
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The delay chain system performs self-characterization by automatically measuring its own delay properties through the iterative component activation process. The system uses its internal circuitry to detect output signal logic values and determine the correct chain length without requiring external measurement equipment or complex design calculations, ensuring reliable interface circuit functionality.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If the delay per stage is not known precisely, then design flexibility is maintained, but it makes it difficult to design the correct chain length

Engineering Contradiction:
Improvedelay chain configurabilityVSAvoidchain length accuracy
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The system changes the parameter of activated component count iteratively to characterize the delay chain. By varying the number of activated components and observing the corresponding output signal logic values, the system accurately determines the delay per stage and correct chain length while maintaining the ability to reconfigure the delay chain for different applications.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7378831B1System and method for determining a delay time interval of components
Publication Date: 2008.05.27 META PLATFORMS INC
  • US7378831B1 patent drawing
  • US7378831B1 patent drawing
  • US7378831B1 patent drawing

AI summary

A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.