Calibrated Delay-Chain Local Oscillator for Accurate Quadrature Phases
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Solution Overview
Problem
Existing local oscillators using odd number frequency dividers fail to generate accurate quadrature outputs due to the lack of quadrature information in their outputs.
Innovation Solution
A local oscillator circuit comprising a phase-locked loop (PLL), an odd number frequency divider, and a calibration circuit with delay chains and an AND gate, low-pass filter, and analog-to-digital converter to generate and calibrate oscillating signals with different phases, ensuring accurate quadrature outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an odd number frequency divider is used, then the circuit structure is simplified, but the quadrature information is lost and accurate quadrature outputs cannot be generated
Solution Approach 1:
The patent segments the frequency division process into two independent paths: an odd number frequency divider path and a delay chain path. The odd number frequency divider (divide by 3) generates a base frequency signal, while the delay chain generates additional phase-shifted signals. This segmentation allows the system to maintain circuit simplicity while recovering quadrature information through the combination of multiple signal paths.
Solution Approach 2:
The delay chain acts as an intermediary component that bridges the gap between the odd number frequency divider output and the required quadrature signals. By introducing controlled delay elements, the system generates intermediate phase-shifted versions of the clock signal that, when combined with the original divided signal, produce accurate quadrature outputs (I and Q signals with 90-degree phase difference).
2Measurement precision
If delay chains are added to generate quadrature signals, then accurate quadrature outputs are achieved, but the circuit complexity increases
Solution Approach 1:
The patent merges the output signals from the odd number frequency divider and the delay chain through logical operations (XOR gates). The in-phase signal (I) is obtained by XORing the divided clock signal with a delayed version, while the quadrature signal (Q) is obtained by XORing the divided clock signal with a differently delayed version. This merging approach generates quadrature signals using simple logic operations rather than complex additional circuitry.
Solution Approach 2:
The patent changes the delay parameters of the delay chains to achieve the desired 90-degree phase difference between I and Q signals. By carefully selecting and adjusting the delay amounts in the delay chains, the system generates accurate quadrature outputs without requiring complex feedback control mechanisms, thus maintaining circuit simplicity while achieving precision.
3Measurement precision
If calibration circuits are added to adjust delay amounts, then precise phase differences are achieved, but the device complexity and calibration time increase
Solution Approach 1:
The calibration circuit automatically adjusts the delay amounts in the delay chains without requiring manual intervention. The system self-calibrates by monitoring the phase relationship between signals and automatically modifying the delay parameters to achieve the desired 90-degree quadrature phase difference. This self-service approach reduces the need for complex external calibration equipment and minimizes calibration time.
Solution Approach 2:
The calibration circuit implements a feedback mechanism where the phase relationship between the generated I and Q signals is continuously monitored and used to adjust the delay chain parameters. This feedback loop ensures that the system maintains accurate quadrature phase difference despite variations in operating conditions, achieving precise phase control through automatic closed-loop adjustment rather than open-loop complex circuitry.
Data Source
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AI summary
A circuit (100) for generating a plurality of oscillating signals with different phases includes a frequency divider (120), a first delay chain (130_1), a second delay chain (130_2) and a calibration circuit (140). The frequency divider (120) is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain (130_1) is arranged for delaying the first frequency-divided input signal, and the second delay chain (130_2) is arranged for delaying the second frequency-divided input signal. The calibration circuit (140) is arranged for controlling delay amounts of the first delay chain (130_1) and the second delay chain (130_2) according to signals within the first delay chain (130_1) or the second delay chain (130_2); wherein output signals of a portion delay cells (210_1 -210_6, 220_1 -220_6) within the first delay chain (130_1) and the second delay chain (130_2) serve as the plurality of oscillating signals with different phases.