Delay Element Chain for Fast Clock Adaptation Under Voltage Droop
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Solution Overview
Problem
Existing clock frequency adaptation circuits face challenges in efficiently handling voltage droops, leading to significant underutilization of circuit resources and requiring large frequency guardbands, which are exacerbated by temperature and voltage variations, and power supply noise.
Innovation Solution
A fast all-digital clock frequency adaptation circuit that reduces frequency guardband by using metastability-containing circuit design to sense voltage changes and adjust the clock phase directly, eliminating additive synchronization delay and allowing for rapid reaction to voltage droops without halting the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock frequency adaptation circuits are used to handle voltage droops, then voltage droop tolerance is improved, but frequency guardband increases and circuit resource utilization decreases
Solution Approach 1:
The circuit performs preliminary sensing of voltage droops and proactively adjusts the clock phase before the droop completes, using a delay element chain to predict and compensate for upcoming voltage variations. This preliminary action allows the system to maintain correct operation without requiring large frequency guardbands.
Solution Approach 2:
A delay element chain is introduced as an intermediary between the voltage sensing mechanism and the clock signal. This intermediary processes the voltage droop information and translates it into appropriate clock phase adjustments, enabling fast adaptation without halting the clock signal and improving overall system efficiency.
2Reliability
If sensing and response mechanisms are added to compensate for voltage variations, then voltage droop tolerance is improved, but synchronization delay increases
Solution Approach 1:
The circuit rushes through the voltage droop event by performing fast phase adjustment of the clock signal using delay element chains. Instead of waiting for complete synchronization, the system skips the traditional multi-cycle synchronization process and achieves compensation within a single clock cycle, minimizing time loss.
3Reliability
If clock frequency is reduced to account for worst-case voltage conditions, then voltage droop tolerance is improved, but attainable clock frequency decreases
Solution Approach 1:
The system dynamically adjusts the clock phase in real-time based on detected voltage droops, rather than using a static reduced frequency. The delay element chains provide dynamic compensation that adapts to the actual voltage conditions, allowing the clock to run at higher frequencies while maintaining reliability during voltage variations.
4Manufacturing precision
If traditional delay compensation techniques are used, then timing accuracy is improved, but response time to fast environmental changes increases
Solution Approach 1:
The circuit performs preliminary sensing and prediction of voltage droops using delay element chains, allowing the system to prepare and execute timing compensation before the actual timing error occurs. This preliminary action maintains high timing accuracy while achieving fast response to environmental changes within a single clock cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables correct operation during frequent and steep voltage droops while minimizing the frequency guardband, allowing for efficient use of circuit resources and fast adaptation to voltage changes, as demonstrated by Spice simulations and VHDL synthesis.
Implementation Method 1
using metastability-containing circuit design to sense voltage changes and adjust the clock phase directly
Data Source
AI summary
A circuit for delaying an electric signal (CI), comprises an input for the electric signal (CI); an input for a control signal (EI); a first storage element (U5) for storing the control signal; a delay element for delaying the electric signal; and an output for the delayed electric signal (CO). According to the invention, the electric signal is delayed, based on the stored control signal. The delay circuit is employed in a fast all-digital clock frequency adaptation circuit for voltage droop tolerance.