Delay Circuit Bias Current Control for PVT Stability
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Solution Overview
Problem
Conventional delay circuits face issues with high power consumption and sensitivity to process, voltage, and temperature (PVT) variations, leading to inaccuracies in electronic device operations.
Innovation Solution
A delay circuit design incorporating a bias current generator and delay generator with current mirrors, capacitors, and Schmitt inverters, utilizing transistors with different channel types to manage bias currents and control delays, reducing power consumption and improving precision against PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional delay circuits are used, then delay function is provided, but power consumption is high due to slow input slew
Solution Approach 1:
The delay circuit is divided into multiple independent delay units (first delay unit, second delay unit, third delay unit) that can operate in parallel or sequence. Each unit has its own input stage, delay element, and output stage, allowing the total delay to be distributed across multiple stages rather than requiring a single high-power stage to handle the entire delay requirement.
Solution Approach 2:
The circuit employs dynamic biasing through current mirrors that automatically adjust bias currents based on operating conditions. The bias current generator uses transistors in different operating regions (saturation and triode) to dynamically control the current flow, optimizing the balance between speed and power consumption at different input slew rates.
2Reliability
If conventional delay circuits are used, then delay function is provided, but delay variations are great due to sensitivity to PVT
Solution Approach 1:
The circuit uses parameter matching through current mirrors to compensate for PVT variations. By mirroring currents through carefully matched transistor pairs and using proportional relationships between different current paths, the circuit maintains consistent delay characteristics despite changes in process, voltage, or temperature. The delay is determined by ratios of matched parameters rather than absolute values.
Solution Approach 2:
The circuit incorporates implicit feedback through the current mirror architecture, where the operation of one transistor stage automatically adjusts the biasing of other stages to maintain equilibrium. The interdependent current relationships create a self-regulating system that resists drift caused by PVT variations.
3Measurement precision
If complex circuit architecture is used to improve precision, then PVT precision is improved, but device complexity increases
Solution Approach 1:
The current mirror structure serves multiple functions simultaneously: it provides bias current generation, performs impedance transformation, enables parameter matching for PVT compensation, and establishes proportional current relationships for delay control. This multi-functionality reduces the need for separate dedicated circuits for each function.
Solution Approach 2:
The circuit combines the bias current generator, delay elements, and output stages into an integrated architecture where current mirrors are shared across multiple delay units. The same transistor pairs and current paths are used to serve both biasing and delay control functions, reducing overall component count and complexity.
Data Source
AI summary
A delay circuit and an electronic system equipped with the delay circuit are provided. The delay circuit includes an input terminal, an output terminal, a bias current generator and a delay generator. The bias current generator is coupled between a first reference voltage and a second reference voltage, and is configured to generate a bias current. The delay generator is coupled between the first reference voltage and the second reference voltage, and is configured to generate a delay of the delay signal relative to the input signal according to the bias current. The bias current generator includes a current mirror, a current module and a transistor. The delay generator includes a first current mirror sub-circuit, a second current mirror sub-circuit, a transistor, a capacitor, a switch circuit and a Schmitt inverter, wherein the output terminal is coupled to the Schmitt inverter to output the delay signal.