Multi-Stage Delay Circuit for Glitch-Free Clock Control

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Solution Overview

Problem

Existing delay lines in integrated circuits generate glitches and incur duty cycle loss when switching delay control signals, and their input load increases linearly with the number of stages, affecting precision and accuracy in high-speed digital systems.

Innovation Solution

A delay circuit comprising N-stage units with four-state gate and inverter circuits, where each stage's input terminals are coupled together, and the output of one inverter circuit is connected to the input of the next stage, eliminating glitches and duty cycle loss by compensating for process, voltage, and temperature offsets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of delay line stages is increased to achieve wide delay adjustment range, then the delay adjustment range is improved, but the input load increases linearly

Engineering Contradiction:

Improvedelay adjustment rangeVSAvoidinput load

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The delay line is segmented into multiple stages, each stage consisting of a delay unit with specific internal structure. By segmenting the overall delay function into manageable stages with controlled input loads, the total input load is distributed and managed effectively while achieving the required delay adjustment range through cascaded stages.

Inventive Principle:

Principle #1Segmentation

2Ease of operation

If existing delay line structure is used to switch delay control signal, then delay control is achieved, but glitch is generated

Engineering Contradiction:

Improvedelay controlVSAvoidglitch

Core Design Contradiction:

Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The delay unit structure is designed with preliminary anti-action to prevent glitch generation. By incorporating specific circuit configurations that anticipate and counteract potential glitch conditions before they occur, the system achieves smooth delay control without generating harmful glitch signals during delay control signal switching.

Inventive Principle:

Principle #9Preliminary anti-action

3Ease of operation

If existing delay line structure is used to switch delay control signal, then delay control is achieved, but duty cycle loss occurs

Engineering Contradiction:

Improvedelay controlVSAvoidduty cycle loss

Core Design Contradiction:

Ease of operationVSLoss of energy

Solution Approach 1:

The delay unit structure converts potential harmful effects into beneficial outcomes. By designing the circuit to compensate for process, voltage, and temperature offsets through its inherent structure, the system transforms what would be sources of duty cycle loss into mechanisms that maintain duty cycle integrity, achieving accurate delay control without duty cycle degradation.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS10965280B2Delay circuit, clock control circuit and control method

Publication Date: 2021.03.30 MONTAGE TECHNOLOGY CO LTD

AI summary

A delay circuit, a clock control circuit and a control method are disclosed. The delay circuit includes N-stage delay units coupled in a chain, the delay unit of each stage comprises the four-state gate circuit and an inverter circuit, an input terminal of a four-state gate circuit and an input terminal of an inverter circuit of each stage are coupled together, another input terminal of the inverter circuit is coupled to an output terminal of the inverter circuit of the next stage; an input signal is coupled to the input terminal of the four-state gate circuit and the inverter circuit of the first stage, and is output with a certain delay of time by sequentially passing through the four-state gate circuit and the inverter circuit of each stage.