Center-Symmetrical Delay Circuit Layout for Consistent NAND Stage Timing
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Solution Overview
Problem
Current semiconductor device layouts face challenges in ensuring consistent delay times across delay stages, leading to inconsistency in signal transmission and inefficient layout design, particularly in Delay Locked Loops (DLLs) where precise phase synchronization of clock signals is crucial.
Innovation Solution
The proposed solution involves a layout design for a delay circuit unit comprising multiple NAND gate circuits arranged in a center-symmetrical structure, with different layout patterns in each row, ensuring consistent delay times and compact integration, thereby improving signal consistency and reducing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional layout designs are used for delay circuits, then the layout area may be reduced, but the delay time consistency across different delay stages deteriorates
Solution Approach 1:
The patent applies asymmetry by using different layout patterns for odd and even delay stages. Specifically, odd delay stages use a first layout pattern while even delay stages use a second layout pattern, creating intentional asymmetry in the layout design. This asymmetric approach allows each stage to be optimized for its specific position in the delay chain, achieving consistent delay times across all stages while maintaining compact area utilization.
2Reliability
If delay circuits are designed with precise phase synchronization, then signal transmission consistency improves, but the layout design complexity increases
Solution Approach 1:
The patent segments the delay circuit into distinct odd and even delay stages, each with dedicated layout patterns. This segmentation allows for targeted optimization of each stage's layout to ensure precise phase synchronization. By dividing the circuit into manageable segments with specific layout requirements, the patent achieves high signal transmission consistency while making the overall design more systematic and controllable.
Solution Approach 2:
The patent applies local quality by assigning different layout patterns to different parts of the circuit based on their position in the delay chain. Odd stages receive a first layout pattern optimized for their specific requirements, while even stages receive a second layout pattern. This localized optimization ensures that each part of the circuit contributes to overall signal consistency without requiring uniform complexity throughout the entire design.
3Ease of manufacture
If uniform layout patterns are used across all delay stages, then layout design simplicity improves, but delay time consistency across stages deteriorates
Solution Approach 1:
The patent introduces dynamics into the layout design by making the layout pattern dependent on the stage position. Rather than using a static uniform pattern, the design dynamically selects between two layout patterns based on whether the stage is odd or even. This dynamic approach allows the layout to adapt to the specific requirements of each stage while maintaining a systematic design process that is relatively easy to manufacture and implement.
Data Source
AI summary
A layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory are provided. The layout of the delay circuit unit includes multiple layout units arranged in an array and each forming a NOT-AND (NAND) gate circuit; here several layout units conforming to a first layout pattern are sequentially arranged in a first row of the array; and several layout units conforming to a second layout pattern are sequentially arranged in a second row of the array; here the first layout pattern is different from the second layout pattern, and the first layout pattern and the second layout pattern are such that the first row and the second row form a center-symmetrical structure.