Delay Circuit Mapping for Monotonic High-Resolution Timing
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Solution Overview
Problem
Existing delay circuits are prone to non-monotonic behavior due to variations in temperature and process, leading to mismatched delay amounts, especially in high-resolution applications, where selecting more delay stages often results in less delay, causing serious mismatches.
Innovation Solution
A delay circuit comprising a delay measurement unit, a delay mapping unit, and a map delay module that generates a mapping table based on a reference signal and clock signal, allowing for the selection of a proper number of delay stages to achieve a desired delay amount, ensuring monotonicity by minimizing delay stage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If more delay stages are selected to increase delay amount, then the delay amount should increase, but due to temperature and process variations the delay amount decreases or becomes non-monotonic
Solution Approach 1:
The patent performs preliminary measurement of actual delay amounts for each delay stage and stores them in a lookup table before normal operation. This preliminary characterization allows the system to compensate for process and temperature variations by selecting delay stages based on pre-measured data rather than nominal values, ensuring monotonic behavior despite manufacturing variations
Solution Approach 2:
The patent implements a feedback mechanism where the delay measurement unit continuously monitors the actual delay amounts and updates the lookup table with corrected values. This feedback loop allows the system to adapt to temperature and process variations in real-time, maintaining monotonicity by adjusting the delay stage selection based on measured performance rather than relying solely on nominal delay values
2Measurement precision
If high resolution delay circuit is designed to achieve precise delay control, then measurement precision is improved, but the circuit becomes more sensitive to variations and non-monotonic behavior
Solution Approach 1:
The patent changes the selection criteria for delay stages from fixed nominal delay values to dynamically selected values based on measured performance parameters. By storing actual delay amounts in a lookup table and selecting stages based on these measured parameters rather than nominal values, the system maintains high resolution while compensating for temperature and process variations that would otherwise cause non-monotonic behavior
3Device complexity
If delay stages are selected based on nominal delay values, then device complexity is reduced, but manufacturing precision and reliability deteriorate due to variations
Solution Approach 1:
The patent introduces a lookup table as an intermediary between the delay stage selection logic and the actual delay stages. This lookup table stores pre-measured delay amounts and allows the selection logic to choose stages based on actual performance rather than nominal values. The intermediary layer adds minimal complexity while dramatically improving delay amount matching accuracy by compensating for process and temperature variations
Data Source
AI summary
A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal.