Switched-Capacitor Delay Circuit Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional 1H-delay circuits using switched capacitor circuits suffer from poor delay characteristics due to increased drain-to-substrate parasitic capacitances, which dull output waveforms and degrade performance.
Innovation Solution
A delay circuit design where switched capacitor units are arranged such that charging and discharging MOS transistors are adjacent, with common drains, reducing parasitic capacitances and improving signal path integrity, and a switching control unit sequences the charging and discharging of capacitive elements to achieve precise delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switched capacitor units are arranged with separate charging and discharging MOS transistors, then the circuit can perform delay function, but drain-to-substrate parasitic capacitances increase causing poor delay characteristics
Solution Approach 1:
The patent combines the charging and discharging functions into a single MOS transistor by making its drain common to both capacitive elements. This merging reduces the number of MOS transistors from two per switched capacitor unit to one, thereby reducing drain-to-substrate parasitic capacitances and improving delay characteristics while maintaining the delay function.
Solution Approach 2:
The single MOS transistor in each switched capacitor unit serves dual functions: charging one capacitive element and discharging another. This multi-functionality is achieved by connecting the drain to both capacitive elements through switching control, eliminating the need for separate charging and discharging transistors and reducing parasitic capacitance.
2Loss of time
If multiple switched capacitor units are used to achieve 1H delay, then the delay time is sufficient, but the number of MOS transistors increases causing increased parasitic capacitance
Solution Approach 1:
Each switched capacitor unit uses a single MOS transistor that performs both charging and discharging operations. This merging reduces the transistor count by 50% compared to conventional designs, thereby reducing total parasitic capacitance while maintaining the required delay time through proper switching control of the reduced transistor set.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively alleviates parasitic capacitance issues, enhancing the delay circuit's output waveforms and delay characteristics, leading to improved performance in video signal processing.
Implementation Method 1
a capacitive element which is connected to sources of the charging and the discharging MOS transistors and which is charged/discharged by turning on/off gates of the charging and the discharging MOS transistors
Data Source
AI summary
A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors; and a switching control unit that performs on/off control of the charging and the discharging of the MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence.