Delay Control Circuit for Phase Alignment Without DLL Lock
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Solution Overview
Problem
Existing delay control circuits struggle with precise timing in digital circuits, particularly in applications with discontinuous reference clock signals, leading to improper delay adjustments and potential data corruption due to phase shifts between clock and strobe signals.
Innovation Solution
A delay control circuit that generates multiple replicas of a reference signal with dedicated time delays, samples these replicas based on the input signal's timing, and selects the appropriate replica to ensure accurate phase alignment, allowing for precise data sampling even without a strict phase relation between the clock and strobe signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay-locked loop (DLL) is used to generate phase-delayed clock signals, then the timing of operations within a clock period can be controlled, but the DLL may lose its lock when the reference clock signal is discontinuous, causing improper delay adjustments
Solution Approach 1:
The patent segments the delay control into multiple discrete delay elements (first delay element, second delay element, etc.) that can be independently controlled. Each delay element can be selectively enabled or disabled to achieve different delay values, allowing the system to maintain accurate timing control even when the reference clock is discontinuous, as the delay settings are preserved in each segment rather than lost in a continuous DLL.
Solution Approach 2:
The patent implements dynamic control of delay elements through control signals that can selectively activate or deactivate specific delay elements based on the state of the reference clock. When the reference clock is present, certain delay elements are activated; when it is absent, different delay elements are activated, allowing the system to adapt its delay configuration dynamically while maintaining reliable operation.
2Adaptability or versatility
If multiple delayed clock signals are provided with a selector switch to accommodate frequency changes, then the device can adapt to varying operating conditions, but the control circuit and tuning operation become complex
Solution Approach 1:
The patent merges multiple delay control functions into a unified structure where delay elements are connected in series/parallel configurations that can be selectively activated. Rather than requiring separate control circuits for each frequency adaptation, the design combines multiple delay paths into a single integrated delay control mechanism that responds to a unified control signal, reducing overall circuit complexity while maintaining adaptability.
Solution Approach 2:
The patent implements preliminary configuration of delay elements during circuit design or initialization, where the delay characteristics of each element are predetermined and fixed. This preliminary action eliminates the need for complex real-time tuning operations, as the system can directly select from pre-configured delay options based on operating conditions, simplifying both the control circuit and tuning operation.
3Productivity
If the reference clock signal arrives in bursts rather than continuously, then data can be accessed in blocks, but the DLL loses its lock between bursts causing insufficient or excessive development time
Solution Approach 1:
The patent implements dynamic control of delay elements based on the bursty nature of the reference clock signal. During active bursts, specific delay elements are activated to provide the required data development time. Between bursts, the system maintains its delay configuration through the persistent state of the delay elements, ensuring that when the next burst arrives, the correct delay is already established, preventing both insufficient and excessive development times.
Solution Approach 2:
The patent provides beforehand cushioning by pre-configuring the delay elements to account for the worst-case data development time requirements. The delay elements are designed with sufficient total delay capacity and are selectively activated to ensure that even in the absence of continuous reference clock signals, the data will have adequate development time before latching, cushioning against timing violations that would occur with DLL lock loss.
Data Source
AI summary
The present invention relates to a delay control circuit and a method of controlling delay of an output signal generating based on an input signal, wherein a plurality of delayed replicas of a reference signal are generated with dedicated time delays with respect to the reference signal and are sampled at a predetermined timing defined by the input signal. One of the delayed replicas is selected based on the output of the sampling means, and the output signal is generated based on the selected replica. Thereby, a predetermined phase relationship can be generated even in cases where no strict phase relation is given between data and reference signal.