Delay Circuit Placement for IC Hold Violations
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Solution Overview
Problem
Circuit designers face challenges in meeting aggressive timing requirements for FPGA circuit designs, as automated CAD tools often fail to resolve timing violations, leading to significant manual effort and resource expenditure.
Innovation Solution
A method is disclosed that identifies driver and load hold violations in integrated circuit designs by determining a first offset from the perimeter of a rectangular region to place a delay circuit outside the region, thereby resolving hold violations with fewer delay circuits, using a computing system to instantiate and connect the delay circuit between the driver and load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay circuits are placed inside the rectangular region between driver and load, then hold violations can be resolved, but the number of delay circuits required increases significantly
Solution Approach 1:
The patent applies dimensionality change by moving the delay circuit placement from the traditional two-dimensional space inside the rectangular region to a three-dimensional approach that utilizes the perimeter and exterior areas. Specifically, delay circuits are placed on the perimeter of the rectangular region or in exterior regions adjacent to the driver or load, fundamentally changing the placement geometry from internal to boundary/exterior positioning. This dimensional shift enables fewer delay circuits to achieve the same timing correction effect.
Solution Approach 2:
The patent implements local quality by creating distinct placement zones with different characteristics: perimeter locations along the rectangular boundary and exterior locations adjacent to driver or load. Each zone provides localized timing correction tailored to the specific hold violation scenario, allowing optimal placement positions to be selected based on the particular geometric and timing constraints of the circuit design.
2Reliability
If more delay circuits are used to resolve hold violations, then timing requirements are met, but device complexity and resource utilization increase
Solution Approach 1:
By transitioning from internal placement to perimeter and exterior placement, the patent reduces the number of delay circuits needed, directly simplifying the overall circuit design. The boundary-based approach creates more efficient timing paths that require fewer correction elements, thereby reducing device complexity while maintaining timing compliance.
3Extent of automation
If automated place and route tools are used, then design process is streamlined, but timing violations cannot be resolved
Solution Approach 1:
The patent implements self-service by providing automated algorithms that specifically target hold violation resolution through intelligent delay circuit placement. The system automatically identifies hold violations, calculates optimal perimeter and exterior placement locations, and inserts the appropriate number of delay circuits, enabling the design tool to resolve its own timing issues without manual intervention while maintaining high automation levels.
Data Source
AI summary
Disclosed approaches for processing a circuit design include identifying a driver and a load having a hold violation in the circuit design. The circuit design is targeted to an integrated circuit (IC) die. The method determines a first offset from a location on a perimeter of a rectangular region of the IC die having corners at locations of the driver and the load such that a length of a signal path from the driver through a first candidate location having placement coordinates that are outside the rectangular region and at the first offset from the location on the perimeter resolves the hold violation. The method determines availability of the first candidate location. In response to determining that the first candidate location is available, the method includes instantiating a delay circuit at the first candidate location and specifying connections that connect the delay circuit between the driver and the load.