Delay Circuit Pulse Shaping for Consistent Output Timing

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Solution Overview

Problem

Conventional delay circuits fail to consistently delay output signals by a predetermined time due to variations in input signal width, often resulting in irregular pulse widths or failure to generate output signals with broad pulse widths.

Innovation Solution

A delay circuit comprising a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit, which generates a pulse signal in response to the input signal's rising edge, activates the output signal after a predetermined time, and adjusts the pulse width of the output signal to ensure uniformity, using a combination of inverters, transistors, and delay devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a conventional delay circuit uses unit delays arranged in an array, then the circuit can delay an input signal by a predetermined time, but the output signal pulse width becomes irregular when the input signal pulse width varies

Engineering Contradiction:
Improvedelay timeVSAvoidoutput pulse width uniformity
Core Design Contradiction:
Loss of timeVSManufacturing precision

Solution Approach 1:

The delay circuit is segmented into multiple functional units: a pulse generating unit that creates a preset-width pulse in response to the rising edge of the input signal, a timing adjusting unit that activates the output signal after a predetermined delay time, and a pulse width adjusting unit that ensures uniform output pulse width. This segmentation allows each unit to perform its specific function independently, resolving the contradiction between achieving predetermined delay time and maintaining uniform output pulse width.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If the input signal has an excessively broad pulse width, then the signal can be processed, but the conventional delay circuit fails to generate an output signal

Engineering Contradiction:
Improveinput signal width toleranceVSAvoidoutput signal generation
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The pulse generating unit performs a preliminary action by generating a pulse signal with a preset width in response to the rising edge of the input signal, regardless of the input signal's pulse width. This preliminary pulse generation ensures that the subsequent timing adjusting unit can reliably activate the output signal after the predetermined delay time, even when the input signal has an excessively broad pulse width, thus maintaining both adaptability and reliability.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If the delay circuit uses a simple array of unit delays, then the device complexity is low, but the circuit cannot maintain consistent delay performance due to input signal variations

Engineering Contradiction:
Improvecircuit structureVSAvoiddelay consistency
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The delay circuit incorporates dynamic control mechanisms through the timing adjusting unit and pulse width adjusting unit. The timing adjusting unit dynamically activates the output signal after a predetermined delay time based on the pulse signal from the pulse generating unit. The pulse width adjusting unit dynamically adjusts the output signal to maintain uniform pulse width. These dynamic adjustments ensure consistent delay performance regardless of input signal variations, achieving reliability without excessive complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8026752B2Delay circuit
Publication Date: 2011.09.27 SK HYNIX INC
  • US8026752B2 patent drawing
  • US8026752B2 patent drawing
  • US8026752B2 patent drawing

AI summary

Disclosed is a delay circuit. The delay circuit includes a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit. The pulse generating unit is configured to generate a pulse signal having a preset width in response to a rising edge of an input signal. The timing adjusting unit is configured to activate an output signal in response to the pulse signal after a predetermined time has lapsed. The pulse width adjusting unit is configured to adjust a pulse width of the output signal in response to the activation of the output signal.