Temperature-Compensated Delay Circuit for Stable RC Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay circuits in memory devices, such as DRAM, experience significant variations in delay time due to temperature changes, leading to temperature-dependent output signals, which is undesirable for maintaining consistent operation across varying temperatures.
Innovation Solution
The proposed delay circuit incorporates a specific configuration of transistors and capacitors, including PMOS and NMOS transistors and resistors, to compensate for temperature variations, ensuring a constant delay time by utilizing a PMOS transistor with a negative temperature coefficient and additional transistors for generating rail-to-rail signals and enhancing pulling low capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional delay circuits with RC timing are used, then the circuit structure is simple, but the delay time varies significantly with temperature changes
Solution Approach 1:
The patent uses a PMOS transistor with negative temperature coefficient whose threshold voltage changes with temperature to compensate for RC timing variations. As temperature increases, the PMOS transistor's threshold voltage decreases, causing it to conduct more strongly and reduce the RC time constant, thereby compensating for the increased delay caused by higher temperature in conventional circuits
Solution Approach 2:
The patent combines PMOS and NMOS transistors with resistive and capacitive elements to create a composite circuit structure. The PMOS transistor with negative temperature coefficient is integrated with the RC timing elements to form a temperature-compensated delay circuit that maintains stable delay characteristics across temperature variations
2Reliability
If temperature compensation is added to maintain constant delay time, then delay time stability improves, but circuit complexity increases
Solution Approach 1:
The patent introduces a PMOS transistor as an intermediary element that mediates between the temperature variations and the RC timing circuit. This transistor acts as a temperature-dependent variable resistor that automatically adjusts the RC time constant to compensate for temperature effects, providing a relatively simple compensation mechanism
Solution Approach 2:
The PMOS transistor with negative temperature coefficient provides automatic temperature compensation without requiring external control circuits. The transistor's inherent temperature-dependent characteristics cause it to self-adjust its conduction level based on temperature, thereby maintaining constant delay time through self-service temperature compensation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in output signals that are largely independent of temperature variations, maintaining consistent delay times across the temperature range from +100° C to −40° C, as demonstrated by convergent timing diagrams, thereby addressing the temperature sensitivity issues in prior art delay circuits.
Implementation Method 1
a first transistor, having: a first terminal, coupled to the output node of the inverting receiver; a control terminal; and a second terminal... the first transistor compensates delay of the inverting receiver as temperature varies
Implementation Method 2
a capacitive element, coupled to the output node of the inverting receiver
Data Source
AI summary
A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting receiver and the resistive element; a first transistor, having lower turned ON voltage at higher temperature; a second transistor, used for generating a rail to rail signals on a terminal of the first transistor; and an output inverter, having an input node coupled to the first transistor and an output node for outputting an output signal of the delay circuit. Further, a third transistor is used for enhancing pulling low of the output signal of the delay circuit.