Delay Circuitry for Mass Storage Power Hold-Up
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Solution Overview
Problem
NAND flash-based solid state drives face data loss and corruption due to power failures, as metadata updates are time-consuming and inefficient, and existing power protection designs increase the risk of power-loss events, leading to potential data loss or drive corruption.
Innovation Solution
A computer device with a delay circuitry system that includes interposer boards with e-fuses and capacitors to delay power shutdown, allowing sufficient time for data from volatile memory to be copied to non-volatile data carriers, using MOSFETs and resistors to manage power distribution and fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is immediately cut off when control logic detects a fault, then the system responds quickly to protect against surges and over-current, but data in volatile cache memory is lost and metadata updates are incomplete
Solution Approach 1:
The system performs preliminary actions by continuously updating metadata in volatile cache memory before power failure occurs. The delay circuitry provides a predetermined time window that allows the system to complete metadata updates and flush cache data to non-volatile storage before power is completely cut off, ensuring data integrity without requiring immediate power cutoff
Solution Approach 2:
The delay circuitry acts as a cushioning mechanism that extends the power cutoff time by a predetermined duration. This cushioning effect allows sufficient time for data to be committed from volatile to non-volatile storage, preventing data loss that would otherwise occur with immediate power cutoff
2Object-affected harmful factors
If both control logic power and drive power are protected by independent e-fuses coupled together, then over-current protection is provided, but power-loss events increase and data loss risk increases
Solution Approach 1:
The power protection system is segmented into independent components: the control logic power path and drive power path are separated with independent e-fuses. The delay circuitry is integrated only in the drive power path, allowing it to provide extended protection without being affected by control logic power failures. This segmentation enables the drive to maintain power and complete data commits even when control logic power is lost
Solution Approach 2:
The delay circuitry serves as an intermediary component between the e-fuse and the drive power. It decouples the immediate power cutoff action from the drive power removal, providing a time buffer that allows data commitment to complete. This intermediary function protects against the harmful effect of immediate power cutoff while maintaining the over-current protection function of the e-fuse
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides reliable power fail protection for non-volatile memory mass storage devices, ensuring data integrity by allowing time for data to be committed to non-volatile memory even during power faults, reducing the risk of data loss and drive corruption.
Implementation Method 1
delay circuitry (e.g., using capacitors) to delay the time power is supplied to the mass storage device
Implementation Method 2
using MOSFETs and resistors to manage power distribution and fault detection
Data Source
AI summary
A delay circuitry is configured to hold up power to a mass storage device after a power fault disables communication of the mass storage device with the host computer. The time delay is sufficient to allow saving of in-flight data from the storage device's volatile cache to the non-volatile media (of the storage device) and to update a metadata table in the non-volatile media.