Variable-Capacitance Delay Circuits for Four-Phase Clock Alignment
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Solution Overview
Problem
Four-phase clocking systems in memory devices face challenges due to phase-to-phase offset issues, where some phases can become out of sync, leading to timing problems that are difficult to mitigate.
Innovation Solution
The use of amplifiers acting as variable capacitors, controlled by adjusting currents through them, to manage delays between buffer stages, effectively mitigating phase-to-phase delay issues by altering the apparent capacitance seen by signal lines through the Miller-effect, and employing differential amplifiers on specific phases to synchronize signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If four-phase clocking is used to increase clock speed, then productivity is improved, but phase-to-phase offset issues cause timing problems that worsen reliability
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller monitors phase-to-phase delays between clock signals and dynamically adjusts delay adjustment circuits to compensate for timing offsets. This closed-loop feedback system maintains phase synchronization even at high clock speeds, resolving the contradiction between productivity improvement and reliability degradation.
Solution Approach 2:
The patent changes the delay parameter of clock signals by adjusting the gain of amplifiers in delay adjustment circuits. By dynamically modifying the delay parameter in response to detected phase offsets, the system maintains reliable phase synchronization while operating at high clock speeds, thus resolving the contradiction between speed and reliability.
2Reliability
If delay adjustment circuits are added to mitigate phase offsets, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent integrates delay adjustment circuits into the existing memory controller architecture, making the controller perform both memory management and clock signal timing adjustment functions. This multi-functionality approach improves phase synchronization reliability without proportionally increasing device complexity, as shared infrastructure is utilized.
Solution Approach 2:
The patent adjusts amplifier gain parameters in delay adjustment circuits to control signal delays. By using simple parameter adjustments rather than complex circuit reconfigurations, the system achieves reliable phase synchronization with minimal increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the clock signals by adjusting the gain of amplifiers, thereby reducing phase-to-phase delays and maintaining clock signal integrity, even under process, voltage, and temperature variations.
Implementation Method 1
The use of amplifiers acting as variable capacitors, controlled by adjusting currents through them, to manage delays between buffer stages, effectively mitigating phase-to-phase delay issues by altering the apparent capacitance seen by signal lines through the Miller-effect
Data Source
AI summary
Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.