Delay Synchronization Clock Circuit for TFT Video Signal Phase Alignment
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Solution Overview
Problem
High-frequency video signals in system displays lead to significant delay differences between clock and video signals on thin-film transistor substrates, making it difficult to integrate clock signal generating circuits due to larger device sizes and increased circuit scales, resulting in poor yield and higher costs.
Innovation Solution
A delay synchronization loop type clock signal generating circuit with a two-stage digital delay line configuration and ring-type shift registers for coarse and fine adjustments, using a low-frequency shift clock to improve operating margins and reduce circuit scale, allowing for phase synchronization and adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a clock signal generating circuit is integrated on a thin-film transistor substrate to synchronize high-frequency video signals, then phase synchronization between clock and video signals is improved, but the circuit scale increases leading to larger device sizes and reduced manufacturing yield
Solution Approach 1:
The delay line is divided into multiple delay units that can be independently controlled by the ring-type shift register. Each delay unit contributes to the total delay time, allowing precise phase adjustment without requiring a single large-scale delay circuit. This segmentation reduces the complexity and area of individual components while achieving the same overall delay function.
Solution Approach 2:
The ring-type shift register dynamically adjusts the delay time by changing the number of delay units activated in the delay line. This dynamic control allows the circuit to adapt to different phase requirements without requiring multiple fixed delay circuits, thereby reducing the overall circuit scale and improving manufacturing yield.
2Measurement precision
If digital circuits are used to configure delay amount setting portions, then delay time can be precisely controlled, but the circuit scale becomes great leading to increased device size and reduced yield
Solution Approach 1:
The patent replaces complex digital delay control circuits with a ring-type shift register that uses simple flip-flop stages. Each flip-flop stage acts as a binary weight element, allowing precise delay control through binary-weighted connections to the delay units. This substitution reduces circuit complexity while maintaining precise delay control capability.
Solution Approach 2:
The patent changes the control parameter from direct digital control of each delay unit to binary-weighted control through the ring-type shift register. By using binary weighting, the circuit achieves precise delay control with fewer control elements, reducing the overall circuit scale while maintaining measurement precision.
3Ease of manufacture
If thin-film transistors are used to form active elements on insulating substrates, then integration is enabled, but device sizes are larger compared to silicon substrates leading to increased circuit scale
Solution Approach 1:
The delay line is segmented into multiple delay units, each with relatively simple transistor circuits. This segmentation allows the use of thin-film transistors without requiring a single large-scale delay circuit, as each segment can be independently optimized for area efficiency while maintaining the overall delay function.
Solution Approach 2:
The ring-type shift register serves multiple functions: it controls the delay amount, provides phase adjustment capability, and enables dynamic reconfiguration. This multi-functionality reduces the need for separate control circuits, thereby reducing the overall circuit scale despite using thin-film transistors with larger device sizes.
Data Source
AI summary
A delay synchronization loop type clock signal generating circuit includes: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring-type shift register for setting the delay time length of the digital delay line by flip-flop output of each stage thereof; and a delay amount control unit for controlling supply of shift clocks to the ring-type shift register, based on phase relation between the first clock signal and the second clock signal.