Delay Clock Adjustment Circuit for PVT-Stable Phase Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay circuits face issues with large circuit area, low accuracy, and sensitivity to process, voltage, and temperature (PVT) variations, which affect signal precision and require longer delay lines for different operation frequencies.
Innovation Solution
An adjusting circuit that generates difference signals based on a reference clock and delay clock signals to determine a target delay clock signal by computing the corresponding number of delay units for a specific phase, allowing for precise adjustment of delay without increasing circuit size and reducing PVT errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog delay circuit is used, then the circuit can generate delay clocks with different phases, but the circuit occupies massive area and provides low accuracy
Solution Approach 1:
The patent replaces the analog delay circuit with a digital delay circuit. The digital approach uses discrete delay stages (inverters) controlled by digital signals instead of continuous analog control, achieving both compact area and high precision through binary control mechanisms
Solution Approach 2:
The delay line is divided into multiple discrete delay stages (N stages), each contributing a fixed delay amount. This segmentation allows precise control of total delay by selecting specific stages, improving accuracy while keeping each stage compact
2Area of stationary object
If a digital delay circuit is used, then the circuit area is reduced, but the delay stages are easily affected by PVT variations causing errors
Solution Approach 1:
The patent introduces a feedback mechanism where the output of the delay line is fed back to the input through a multiplexer. This allows the system to monitor and adjust delay stages dynamically, compensating for PVT variations and maintaining stable performance
Solution Approach 2:
The delay circuit incorporates dynamic control through multiplexers that can selectively activate different delay stages based on operating conditions. This dynamic reconfiguration allows the circuit to adapt to PVT changes and maintain optimal performance
3Adaptability or versatility
If the delay line is extended to reach higher operation frequencies, then the frequency range is expanded, but the circuit area increases
Solution Approach 1:
The patent uses multiplexers to dynamically select and activate different numbers of delay stages based on the required operation frequency. This allows a single compact delay line to serve multiple frequency ranges by selectively enabling N, N-1, N-2, etc. stages, avoiding the need for physically longer delay lines
Solution Approach 2:
The delay line is designed to be multi-functional, capable of operating at multiple frequencies by varying the number of active stages. The same physical delay line structure serves different frequency requirements through selective stage activation, eliminating the need for separate delay lines for different frequency ranges
Data Source
AI summary
Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals, and the adjusting circuit includes: a difference signal generating circuit, for generating a plurality of difference signals according to a reference clock signal and the delay clock signals; a delay processing circuit, coupled to the difference signal generating circuit, for determining the target delay clock signal by computing a corresponding number of delay units for a specific phase of the reference clock signal according to the difference signals; wherein the target delay clock signal is one of the delay clock signals.