Delay Code Generation Circuit for PVT-Stable Internal Clock Timing
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Solution Overview
Problem
Semiconductor devices face errors in delay intervals due to variations in Process, Voltage, and Temperature (PVT), which existing delay circuits struggle to accurately manage.
Innovation Solution
A semiconductor device is designed with a delay code generation circuit that adjusts shifting codes based on phase comparisons between internal and delayed clocks, generating first and second delay codes to offset errors in delay intervals, thereby stabilizing the delay circuit's performance across varying PVT conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay circuit is used to secure delay intervals for internal operations, then the semiconductor device can perform sequential operations, but errors in delay intervals occur due to PVT variations
Solution Approach 1:
The patent implements a feedback mechanism where the phase detection circuit continuously monitors the phase difference between the delayed clock and the second internal clock, and the shifting control signal generation circuit adjusts the shifting code based on this feedback to maintain accurate delay intervals despite PVT variations
Solution Approach 2:
The patent dynamically changes the shifting code parameter based on detected phase differences, allowing the delay circuit to adapt its delay characteristics in response to PVT variations and maintain reliable operation across different conditions
2Measurement precision
If a phase detection circuit and shifting control mechanism are added to adjust delay codes dynamically, then delay interval accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces a phase detection circuit as an intermediary component that mediates between the delayed clock and the second internal clock, providing phase difference information that enables precise delay adjustment without requiring direct complex control logic
Solution Approach 2:
The patent divides the delay adjustment function into separate modular components: a delayed clock generation circuit, a phase detection circuit, a shifting control signal generation circuit, and a code latch circuit, allowing each to be optimized independently while working together to achieve accurate delay control
Data Source
AI summary
A semiconductor device includes a delay code generation circuit configured to adjust a shifting code for delaying a first internal clock, by comparing phases of a second internal clock and a delayed clock, the delayed clock generated by delaying the first internal clock, and configured to generate a first delay code and a second delay code from the shifting code.