Delay Comparator ADC Stages for Clockless High-Speed Conversion
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Solution Overview
Problem
Analog-to-digital converters face challenges in operating at high speed with low power consumption and minimal meta-stability while occupying a small area, as existing solutions often require large resources and are prone to meta-stability issues.
Innovation Solution
The proposed analog-to-digital converter system employs a delay comparator with a logic gate that generates digital and delay signals based on the order and timing of input signals, allowing for asynchronous operation without a clock, and uses a combiner to process signals across multiple stages, reducing the need for large resources and minimizing meta-stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional analog-to-digital converter designs are used, then conversion functionality is achieved, but the device occupies large area and consumes high power
Solution Approach 1:
The patent replaces conventional clocked sequential logic with an asynchronous delay-based mechanism. The converter uses delay elements and delay comparators that operate without a clock signal, allowing the system to self-regulate based on signal propagation delays. This substitution eliminates the need for clock distribution networks and reduces synchronization overhead, achieving high-speed conversion with reduced area and power consumption
2Reliability
If clocked operation is used to ensure synchronization, then timing accuracy is improved, but meta-stability issues increase
Solution Approach 1:
The asynchronous delay comparator operates autonomously without external clock control. When input signals arrive, the delay element introduces a predetermined delay to one signal, and the delay comparator automatically determines which signal arrived first by comparing the delayed signal with the other input signal. The system self-regulates its operation based on the actual arrival times of input signals, eliminating meta-stability issues associated with clocked synchronization while maintaining ease of operation
3Measurement precision
If delay comparators are used to determine signal order, then timing information is captured accurately, but device complexity increases
Solution Approach 1:
The patent merges the delay element and delay comparator into a single integrated functional unit. The delay element receives first and second input signals and outputs a delayed version of one signal, which is then directly fed to the delay comparator along with the other input signal. This merging eliminates the need for separate delay circuits and comparator logic, reducing device complexity while maintaining accurate timing measurement capability
Data Source
AI summary
An analog-to-digital converter has a logic gate for generating an output signal having a delay corresponding to a delay between input signals. The logic gate includes inputs for receiving the input signals, and an output for outputting the output signal. A delay comparator generates a digital signal representative of the order of the input signals, and generates a delay signal having a delay corresponding to the delay between the input signals. The delay comparator has inputs for receiving the input signals, a digital output for outputting the digital signal, and a delay output for outputting the delay signal. A delay-based analog-to-digital converter, with a front stage and successive residual stages, is also disclosed. A delay comparator having merged comparator, sign-out, and delay-out circuits, and which may be operated within one of successive stages, without a clock, is also disclosed.