Delay Compensation Circuit for SMPS Dead Time Reduction
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Solution Overview
Problem
Existing driver stages in switched-mode power supplies (SMPS) face inefficiencies due to prolonged dead time, which increases losses, especially at higher switching frequencies and low output voltages, and are unable to effectively compensate for delays in comparator and logic paths, leading to suboptimal performance.
Innovation Solution
The implementation of a delay compensation circuit with a threshold locked loop (TLL) that aligns the turning on of power transistors with the zero-crossing of the voltage waveform, using sampler circuits and integrators to generate timing signals that compensate for delays, thereby minimizing dead time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dead time is extended to ensure proper switching transitions, then reliability of power transistor operation is improved, but energy loss increases
Solution Approach 1:
The patent dynamically adjusts the dead time parameter based on operating conditions. The delay compensation circuit modifies the effective dead time by generating compensation signals that advance or delay switching transitions, transforming the fixed dead time into a variable parameter that adapts to minimize energy loss while ensuring reliable transistor operation.
Solution Approach 2:
The patent employs feedback mechanisms where the delay compensation circuit monitors the actual switching transitions and comparator delays, then adjusts the timing signals accordingly. This closed-loop approach ensures that the dead time is optimized in real-time based on the actual behavior of the power transistors and control circuitry.
2Productivity
If switching frequency is increased to improve productivity, then output voltage regulation speed is improved, but dead time losses become more significant
Solution Approach 1:
The patent changes the dead time parameter dynamically with switching frequency. As frequency increases, the delay compensation circuit adjusts the timing to reduce dead time proportionally, ensuring that energy loss does not scale linearly with frequency improvement.
3Measurement precision
If comparator reference voltages are set closer to zero to improve measurement precision, then zero-crossing detection accuracy is improved, but susceptibility to noise increases
Solution Approach 1:
The patent introduces an intermediary delay compensation circuit between the comparators and the switching control. This intermediary layer processes the comparator outputs with controlled delays that compensate for circuit propagation delays, allowing the use of low threshold voltages for accurate zero-crossing detection while filtering out noise through the deliberate timing adjustments.
Data Source
AI summary
An integrated circuit includes a delay compensation circuit (221, 222) that further includes a terminal for receiving a varying signal from a circuit external to the integrated circuit; a sampler circuit that samples and holds a present value of the varying signal at each occurrence of a transition in a digital signal; an integrator, coupled to the sampler circuit, that integrates a voltage difference between a sample of the varying signal and a reference signal, and that outputs results of the integration, wherein a time constant of the integrator is greater than a period of the varying signal; a waveform generator that generates a decreasing voltage in response to a transition in a second digital signal; and a comparator that has one input terminal for receiving the decreasing voltage, an inverted input terminal for receiving the results, and an output terminal for outputting a signal that generates an output signal.