Configurable Delay Counter for Variable-Frequency Clock Timing
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Solution Overview
Problem
Existing communication protocols with finite state machines face complexity when dealing with programmable clock frequencies, as they require extensive logic to implement comparators for arbitrary clock frequencies, especially when a large number of bits and count values are involved.
Innovation Solution
A configurable counter that increments or decrements a stored value by a configurable amount based on the clock cycle period, allowing for multiple delay times and using a comparison circuit to check against a fixed value, enabling efficient operation across various clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a full comparator or subtractor is implemented to check against arbitrary count values, then the state machine can accommodate any clock frequency, but the logic complexity and resource requirements become prohibitive
Solution Approach 1:
The patent segments the delay requirement into fixed time units rather than requiring direct comparison of arbitrary clock cycle counts. The delay is specified in terms of a fixed number of time units, and the system automatically calculates the corresponding clock cycle count based on the actual clock frequency. This segmentation transforms a complex arbitrary-value comparison problem into a standardized fixed-unit measurement problem.
Solution Approach 2:
The patent changes the parameter representation from direct clock cycle counts to fixed time unit measurements. Instead of comparing counter values against frequency-specific thresholds, the system uses a frequency-independent time unit parameter that remains constant across all clock frequencies. The conversion from time units to actual clock cycles is performed automatically based on the configured frequency, eliminating the need for complex comparators.
2Device complexity
If discrete frequency support is implemented with fixed counter limits, then the logic is simple for those frequencies, but the system cannot accommodate arbitrary or additional frequencies
Solution Approach 1:
The patent creates a universal delay mechanism that works across all clock frequencies through a single standardized approach. The fixed time unit parameter and automatic conversion mechanism provide multi-functionality, allowing the same hardware and logic to handle any frequency within the supported range without requiring frequency-specific configurations or multiple dedicated circuits.
Solution Approach 2:
The patent introduces dynamic adaptation where the system automatically adjusts the counter limit based on the configured clock frequency. Rather than having static, frequency-specific counter values, the system dynamically calculates the appropriate counter limit from the fixed time unit parameter and the actual clock frequency, enabling flexible frequency support with simple underlying logic.
3Adaptability or versatility
If a programmable register is used to store frequency-specific counter limits, then any frequency can be supported, but the comparison logic still requires extensive resources for large count values
Solution Approach 1:
The patent extracts the frequency-specific information from the comparison logic and places it in the configurable parameter (fixed time units). By separating the frequency-independent time unit specification from the frequency-dependent clock cycle calculation, the system eliminates the need for complex comparators. The comparison is simplified to checking against a fixed time unit value, while the frequency adaptation is handled by the parameter conversion mechanism.
Data Source
AI summary
In certain arrangements and methods, a reset-able counter (100) produces multiple delay times as required by, for example, a finite state machine. The counter (100) counts a stored value by a configurable amount. That configurable amount is determined based upon the period of a clock cycle divided by a desired time unit. The value held by the counter does not represent a count of clock cycles, but rather a count of time units. In other aspects, a device generates fixed delays derived from a variable frequency input clock. The device includes a count circuit (100) and a comparator (114, 116). The number of time-units between consecutive clock edges of the input clock is stored, and the count circuit changes a current-count value by a corresponding amount, with the change being responsive to a clock edge of the input clock. The comparator (114, 116) compares the current-count value to a fixed value that represents a fixed delay time.