Delay Device for Switching Sequence Compensation in Power Converters
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Solution Overview
Problem
Converter systems, particularly those with half-bridge circuits like 3-level ANPC, experience delays in switching transitions, leading to reduced modulation levels, increased power losses, and harmonic distortion in the output voltage due to delayed switching edges.
Innovation Solution
A control system that includes a delay device to adjust switching times in power electronic systems, ensuring a constant delay between switching sequences and output voltage changes, thereby compensating for varying delays in switching transitions and optimizing output voltage waveform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If switching transitions are performed in half-bridge circuits, then power conversion function is achieved, but varying delays occur between switching signals and output voltage changes
Solution Approach 1:
The patent applies preliminary action by detecting the subsequence of switching transitions before executing them, determining the appropriate delay value in advance, and then applying this delay to compensate for the varying delays that will occur during actual switching. This allows the system to pre-calculate and pre-adjust for the timing variations that will occur during power conversion operations.
Solution Approach 2:
The patent changes the timing parameter of switching signals dynamically based on the detected subsequence. By identifying different subsequences of switching transitions and assigning different delay values to each, the system adjusts the timing parameters adaptively to compensate for the varying delays inherent in different switching scenarios, thereby maintaining precise timing control.
2Device complexity
If switching edges are delayed, then output voltage waveform accuracy is reduced, but simpler control logic can be used
Solution Approach 1:
The patent implements feedback by detecting the actual subsequence of switching transitions that occur in the half-bridge circuit and using this detection information to determine the appropriate delay value. This closed-loop approach ensures that the delay compensation is based on the actual switching behavior, maintaining high waveform accuracy while using relatively simple control logic that adapts to different operating conditions.
3Power
If constant power flow is maintained with delayed switching, then higher fundamental frequency amplitude is required, but this increases power losses
Solution Approach 1:
By determining the appropriate delay value in advance based on the detected subsequence, the system compensates for switching delays before they affect the output power. This preliminary compensation maintains the intended power flow characteristics without requiring increased fundamental frequency amplitude, thereby avoiding additional power losses.
4Productivity
If switching transitions cause varying delays, then modulation level is reduced, but the system structure remains simple
Solution Approach 1:
The patent changes the timing parameter of switching signals based on the detected subsequence, assigning different delay values to different switching scenarios. This dynamic parameter adjustment compensates for the varying delays caused by different switching transitions, maintaining high modulation levels while working within the existing simple system structure without requiring complex hardware modifications.
Data Source
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AI summary
A controller (12) for a power electronic system (10) comprises a control device (14) for generating a switching sequence (38) for a semiconductor circuit (26) of the power electronic system (10), wherein the switching sequence (38) comprises a sequence of switching times for switching between switching states of the semiconductor circuit (26); a delay device (16) for delaying switching times from the switching sequence (38); and a switching device (20) for generating switching signals (34) for the semiconductor circuit (26) from the switching sequence (40) modified by the delay device (16); wherein the delay device (16) is configured to detect a subsequence of the switching sequence (38) ending in a switching time and to determine a delay (52) for the switching time from the subsequence.