Delay-Enhanced Inverter Circuit Using Miller Effect Feedback
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Solution Overview
Problem
The challenge in the semiconductor industry is to design integrated circuits (ICs) with improved performance while maintaining a small footprint, as existing designs face issues with signal propagation delay and power consumption, particularly in the context of increasing transistor density and reduced component sizes.
Innovation Solution
The introduction of a delay-enhanced inverter circuit (DE-inverter) that incorporates a capacitive device feedback-coupled between nodes, exploiting the Miller Effect to enhance signal propagation delay without increasing the circuit's footprint, combined with a buffer structure that balances the number of PMOS and NMOS transistors to reduce power consumption and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If transistor density is increased and component sizes are reduced, then IC size is reduced, but signal propagation delay increases
Solution Approach 1:
The patent introduces a feedback mechanism using a capacitive device connected between the input and output nodes of the inverter circuit. This feedback path allows the output signal to influence the input, creating a delay-enhanced effect that compensates for the reduced propagation delay caused by miniaturization.
Solution Approach 2:
The patent modifies the electrical parameters of the inverter circuit by adding the capacitive device, which changes the time constant and propagation delay characteristics of the circuit without physically enlarging the component size.
2Loss of time
If delay-enhanced inverter circuit is used, then signal propagation delay is improved, but power consumption increases
Solution Approach 1:
The patent applies delay enhancement selectively to specific inverter circuits within the buffer structure rather than uniformly across all circuits. The buffer structure includes both delay-enhanced inverters (with capacitive devices) and non-delay-enhanced inverters, allowing localized optimization of delay where needed while minimizing overall power consumption.
3Use of energy by moving object
If buffer structure with balanced PMOS and NMOS transistors is used, then power consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent designs a universal buffer structure that can be implemented with balanced PMOS and NMOS transistor configurations. This standardized approach allows the same buffer design to be reused throughout the IC, reducing overall complexity despite the increased transistor count per buffer unit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved performance with reduced power consumption and leakage, while maintaining a comparable footprint to non-delay-enhanced circuits, thereby addressing the limitations of existing designs in terms of signal propagation and transistor density.
Implementation Method 1
incorporates a capacitive device feedback-coupled between nodes, exploiting the Miller Effect to enhance signal propagation delay
Data Source
AI summary
A delay-enhanced inverter circuit (DE-inverter) includes: a non-delay-enhanced inverter circuit (NE-inverter) having an output at a first node and an input at a second node; and a capacitive device feedback-coupled between the first node and the second node. The capacitive device includes: a first positive-channel metal-oxide (PMOS) field-effect transistor (FET) (PFET) feedback-coupled between the first node and the second node, the first PFET having a capacitor-configuration; and a first negative-channel metal-oxide (NMOS) FET (NFET) feedback-coupled feedback-between the first node and the first reference voltage, the first NFET having a capacitor-configuration.