On-Chip Delay Fault Testing for 3D Chip I/O
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Solution Overview
Problem
In 3D chip stacks, testing chip input/output (I/O) connections is challenging due to the high cost and potential damage of probe testing, and existing methods introduce significant parasitic capacitance, which degrades yield and increases power consumption.
Innovation Solution
An on-chip delay fault testing circuit using a low-capacitance loop-back circuit couples the output to the input, delaying sampling to detect delay faults without external probes, minimizing parasitic capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If probe testing is used to test chip I/O connections, then testing can be performed, but the probe card cost increases, microbumps may be damaged, and tester equipment cost increases
Solution Approach 1:
The chip performs self-testing through an on-chip loop-back circuit that connects the output to the input, allowing the device to test itself without external probe equipment. This eliminates the need for expensive probe cards and complex tester equipment while maintaining testing capability.
Solution Approach 2:
An on-chip loop-back circuit serves as an intermediary element that enables testing by providing an internal signal path from output to input, replacing the need for external probe testing infrastructure.
2Measurement precision
If conventional loop-back testing is used, then delay faults can be detected, but parasitic capacitance increases causing delay degradation and power consumption increase
Solution Approach 1:
The patent changes the capacitance parameter of the loop-back circuit by using a specialized low-capacitance design. This maintains the ability to detect delay faults through the loop-back path while minimizing the parasitic capacitance that would otherwise degrade signal delay and increase power consumption.
3Measurement precision
If conventional loop-back testing is used, then delay faults can be detected, but signal delay increases due to parasitic capacitance
Solution Approach 1:
The patent optimizes the capacitance parameter of the loop-back circuit to minimize signal delay. By using a low-capacitance design, the signal can traverse the loop-back path for testing purposes without experiencing excessive delay that would affect both testing accuracy and normal operation.
4Productivity
If more high speed test channels are used in tester equipment, then testing capability improves, but equipment cost increases
Solution Approach 1:
The chip performs self-testing using internal resources, eliminating the need for external high-speed test channels and complex tester equipment. This approach maintains testing productivity while significantly reducing equipment complexity and cost.
Data Source
AI summary
An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.