Delay-Folding ADC Circuit for High-Speed RF Signal Conversion
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Solution Overview
Problem
Analog-to-digital converter systems in direct radio-frequency sampling receivers face challenges in efficiently converting high-frequency analog signals into digital codes at high speeds, particularly in accurately selecting and processing delay signals for effective signal processing.
Innovation Solution
A conversion and folding circuit that includes a voltage-to-delay converter block with preamplifiers and logic gates, such as OR and AND gates, to transform voltage signals into delay signals, allowing for the selection of earlier-arriving and later-arriving delay signals, which can be input into an analog-to-digital converter, enabling efficient signal processing and reducing meta-stability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage-to-delay conversion with multiple preamplifiers is used, then signal processing accuracy is improved, but device complexity increases
Solution Approach 1:
The voltage-to-delay converter is divided into multiple preamplifiers (first preamplifier, second preamplifier, etc.), each handling different voltage ranges. This segmentation allows parallel processing of voltage signals through multiple paths, improving measurement precision while managing complexity through modular design
Solution Approach 2:
The patent transitions from voltage domain to delay domain by converting voltage signals into time-delayed signals. This dimensional change from voltage amplitude to time delay provides a new processing dimension that improves signal discrimination accuracy without proportionally increasing device complexity
2Productivity
If multiple delay signals are processed through folding block, then productivity is improved, but device complexity increases
Solution Approach 1:
The folding block dynamically selects and processes delay signals based on their arrival times. Earlier-arriving delay signals are processed through first logic gates while later-arriving signals are processed through second logic gates, enabling dynamic adaptation to different signal conditions and improving processing productivity
Solution Approach 2:
The system prepares multiple delay signal paths in advance through the voltage-to-delay converter block with multiple preamplifiers. By pre-establishing these parallel delay paths, the folding block can quickly select and process the appropriate delay signals without sequential processing delays, improving productivity
3Productivity
If high-speed operation is implemented, then productivity is improved, but reliability deteriorates due to meta-stability
Solution Approach 1:
The folding block segments the processing of delay signals into distinct paths: first logic gates for earlier-arriving signals and second logic gates for later-arriving signals. This segmentation prevents signal conflicts and meta-stability conditions that would occur in high-speed operation with undifferentiated signal processing paths
Solution Approach 2:
The patent introduces delay signals as an intermediary mechanism that temporalizes voltage comparisons. By converting simultaneous voltage comparisons into sequential delay-based selections, the system mediates between high-speed operation requirements and meta-stability avoidance, allowing fast operation without direct conflicting signal interactions
Data Source
AI summary
An RF receiver including: a low noise amplifier adapted to be coupled to an antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit including: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.