Delay-Folding ADC Signal Routing for High-Speed RF Sampling

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Solution Overview

Problem

Existing analog-to-digital converters face challenges in efficiently processing high-frequency analog signals, particularly in direct radio-frequency sampling receivers, where they need to operate at high speeds and avoid processing loss by ensuring critical delay signals are not combined in the same logic gate.

Innovation Solution

A delay-based analog-to-digital converter system that uses logic gates, delay comparators, and a multiplexer system to process delay signals from preamplifiers, selecting the most informative signals to generate digital output codes without loss of gain, by ensuring no two critical delay signals from the same preamplifier are processed together.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple delay signals are processed together in the same logic gate to increase processing capacity, then productivity is improved, but measurement precision deteriorates due to processing loss of critical delay signals

Engineering Contradiction:
Improveprocessing capacityVSAvoiddelay signal accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent divides the processing of delay signals by ensuring that critical delay signals from the same preamplifier are processed in separate logic gates rather than combined together. This segmentation prevents processing loss while maintaining overall system productivity through parallel processing of non-critical signal combinations.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the converter operates at high speed to meet RF sampling requirements, then productivity is improved, but measurement precision deteriorates due to increased processing loss

Engineering Contradiction:
Improveconversion speedVSAvoidsignal conversion accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by pre-identifying and protecting critical delay signal paths before processing occurs. By determining which delay signals are critical in advance and routing them through dedicated logic gates, the system maintains high conversion speed while preventing processing loss that would otherwise occur at high operating speeds.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If more logic gates are used to process all delay signals to improve measurement precision, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvedelay signal processing accuracyVSAvoidlogic gate configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by providing enhanced processing protection only for critical delay signals rather than uniformly processing all signals with the same level of protection. This selective approach improves measurement precision for critical signals while avoiding the unnecessary complexity that would result from applying the same protection to all signals.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11387840B1Delay folding system and method
Publication Date: 2022.07.12 TEXAS INSTRUMENTS INC
  • US11387840B1 patent drawing
  • US11387840B1 patent drawing
  • US11387840B1 patent drawing

AI summary

A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.