Delay-Domain Folding Circuit for High-Speed RF ADC Conversion
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Solution Overview
Problem
Analog-to-digital converter systems in direct radio-frequency sampling receivers face challenges in efficiently converting high-frequency analog signals into digital codes at high speeds, particularly in accurately selecting and processing delay signals for effective signal processing.
Innovation Solution
A conversion and folding circuit that includes voltage-to-delay converters and logic gates to select earlier-arriving and later-arriving delay signals, allowing for the generation of delay signals that can be input into an analog-to-digital converter, utilizing preamplifiers and Boolean logic gates to process signals in the delay domain and select relevant delay information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage-to-delay converters and logic gates are used to select delay signals, then signal processing speed is improved, but circuit complexity increases
Solution Approach 1:
The circuit is divided into multiple independent voltage-to-delay converter blocks, each handling specific voltage ranges. Each block contains preamplifiers and logic gates that operate independently to convert and select delay signals, enabling parallel processing that increases speed while keeping individual block complexity manageable
Solution Approach 2:
The patent transitions from voltage-domain processing to delay-domain processing by converting voltage signals into time-delay signals. This dimensional change allows the use of simple logic gates (AND, OR) to perform complex signal selection operations, improving processing speed while maintaining relatively simple circuit structures
2Measurement precision
If multiple preamplifiers and logic gates are used for delay signal selection, then measurement precision is improved, but power consumption increases
Solution Approach 1:
Each voltage-to-delay converter block is designed with specific preamplifiers and logic gates optimized for particular voltage input ranges. The logic gates are configured to activate only when specific voltage conditions are met, enabling precise delay signal selection while minimizing the number of active components at any given time, thus reducing overall power consumption
3Productivity
If high-speed operation is implemented in ADC system, then productivity is improved, but signal noise increases
Solution Approach 1:
The patent replaces traditional high-speed voltage comparison mechanisms with a delay-domain processing approach using logic gates. This substitution enables high-speed operation because logic gates can operate at higher frequencies with lower noise generation compared to analog comparators, thus improving productivity while minimizing signal noise
Data Source
AI summary
A conversion and folding circuit includes a voltage-to-delay converter block, including preamplifiers, for converting a voltage signal into delay signals, and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals. If desired, the logic gates may include odd and even chains for outputting delay signals to first and second analog-to-digital converters. If desired, the conversion and folding circuit may include first and second chains, and a chain selection circuit for selectively outputting a delay signal from a desired one of the first and second chains.