Two-Stage Delay Inverter for Stable TFT Signal Timing
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Solution Overview
Problem
In polysilicon or amorphous silicon processes for TFTs on insulating substrates, transistor characteristics like threshold voltage and mobility exhibit large variations, leading to increased power consumption and larger transistor sizes, which are not suitable for low power consumption and narrow frame designs.
Innovation Solution
A delay circuit with a series and parallel configuration of transistors of identical and different channel types, along with a hysteresis characteristic generating circuit, is used to accommodate transistor variations and achieve low power consumption and a narrower frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If typical CMOS inverter circuits are used for delay buffer, then the circuit achieves simple configuration and low power consumption, but the delay amount varies significantly due to transistor characteristic variations
Solution Approach 1:
The delay buffer is segmented into multiple delay units, each consisting of a specific transistor configuration (first transistor connected to VDD, second transistor connected to VSS, with third transistor controlling the delay). This segmentation allows the delay characteristics to be controlled by specific transistor types rather than being influenced by variations in all transistor types, thereby improving delay stability while maintaining simple circuit configuration.
2Reliability
If transistor size is increased to accommodate characteristic variations, then the circuit achieves better performance margin, but the frame size increases and power consumption increases
Solution Approach 1:
The invention applies local quality by making the delay characteristic dependent on specific transistor types (first transistor for P-channel or N-channel, second transistor for opposite channel) rather than requiring all transistors to have uniform large sizes. This allows different parts of the circuit to have different functions: the delay-determining transistors can be small while providing sufficient performance margin, while other transistors serve supporting roles. This reduces overall frame size while maintaining performance margin.
3Reliability
If transistor size is increased to accommodate characteristic variations, then the circuit achieves better performance margin, but power consumption increases
Solution Approach 1:
The invention enables different parts of the circuit to have different functions with optimized sizing. The delay-determining transistors (first and second transistors) can be sized to provide adequate performance margin for delay control, while third transistors and other supporting elements can be sized for minimal power consumption. This local optimization reduces overall power consumption while maintaining performance margin.
4Measurement precision
If delay buffer circuits are used to detect transistor characteristics, then the detection accuracy improves, but the circuit area increases
Solution Approach 1:
The delay buffer is divided into multiple delay units with specific transistor configurations that isolate the delay measurement to particular transistor types. This segmentation allows accurate detection of transistor characteristics (threshold voltage, mobility) by measuring delay in a controlled configuration, while using multiple units to average out variations and improve detection accuracy without requiring a single large circuit.
Solution Approach 2:
Multiple delay units are combined to provide both accurate characteristic detection and improved statistical accuracy through averaging. The invention merges the functionality of delay measurement and characteristic detection into a unified compact structure, reducing overall circuit area while maintaining or improving detection accuracy.
Data Source
AI summary
Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor.