Delay-Latch Multi-Phase Frequency Divider Without Illegal States
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Solution Overview
Problem
Existing multi-phase frequency dividers require additional initialization and supervision logic to prevent illegal states, which increases gate count, power consumption, and decreases speed, especially in Johnson counter configurations with multiple flip-flops.
Innovation Solution
A multi-phase frequency divider with a Johnson counter configuration that uses a maximum of two flip-flops and additional delay latches to generate staggered output phases without the need for initialization or supervision logic, ensuring no illegal states and maintaining operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Johnson counter configuration with multiple flip-flops is used to generate multi-phase clocks, then the number of output phases is increased, but gate count, power consumption increase and speed decreases
Solution Approach 1:
The patent divides the frequency division function into multiple stages, with each stage using a simple counter configuration. Instead of using one complex Johnson counter with multiple flip-flops, the system uses multiple simpler counter circuits that process the clock signal in sequential stages, thereby reducing the gate count and complexity in each individual circuit while maintaining the ability to generate multiple phases.
Solution Approach 2:
The patent transitions from generating multiple phases within a single counter circuit to generating phases across multiple sequential stages. This dimensional shift from spatial complexity (multiple flip-flops in parallel) to temporal sequencing (multiple stages in sequence) reduces the gate count and power consumption while preserving the multi-phase output capability.
2Adaptability or versatility
If Johnson counter configuration with multiple flip-flops is used to generate multi-phase clocks, then the number of output phases is increased, but power consumption increases
Solution Approach 1:
By segmenting the frequency division into multiple simple stages, each stage consumes less power than a single complex Johnson counter would require. The total power consumption is distributed across stages, with each stage using minimal logic elements, thereby reducing overall power consumption while maintaining multi-phase output capability.
Solution Approach 2:
Each counter stage uses a minimal, simple configuration that is easy to implement and consumes low power. Rather than investing in a complex, high-power Johnson counter, the system uses multiple inexpensive, low-power counter stages that achieve the same functional result with significantly reduced power consumption.
3Adaptability or versatility
If Johnson counter configuration with multiple flip-flops is used to generate multi-phase clocks, then the number of output phases is increased, but operation speed decreases
Solution Approach 1:
By dividing the frequency division into multiple simple stages, each stage can operate at high speed with minimal logic delay. The sequential nature of the stages allows each to complete its operation quickly before passing to the next stage, maintaining high overall operation speed while generating multiple phases.
Solution Approach 2:
The patent uses periodic clock signals to drive each counter stage in sequence, with each stage processing the signal at optimal timing intervals. This periodic action ensures that each simple counter stage can operate at maximum speed without the timing conflicts that would arise in a complex simultaneous multi-flip-flop Johnson counter.
4Reliability
If additional initialization and supervision logic is added to prevent illegal states, then reliability is improved, but gate count, power consumption increase and speed decreases
Solution Approach 1:
The simple counter configuration inherently avoids illegal states through its basic design. Each counter stage naturally progresses through valid states in sequence, and the minimal logic required to implement the counter automatically prevents illegal state transitions. This self-service approach eliminates the need for additional initialization and supervision logic, maintaining reliability without increasing gate count.
Data Source
AI summary
A multi-phase frequency divider comprises first and second latches configured to receive a first input clock having a first frequency and a first phase, wherein the second latch receives the inverted first input clock. The first and second latches generate a plurality of output clocks each having a frequency that equals the first frequency divided by a predetermined divider ratio. The plurality of output clocks each have different phases staggered from the first phase. The frequency divider also comprises at least a first delay latch electrically connected between the first and second latches. The first delay latch is configured to generate, based on an output clock generated by the first latch and a second input clock at the first frequency and a second phase, two delayed output clocks. These two delayed output clocks have a frequency that equals the first frequency divided by the predetermined ratio with different staggered phases.