Delay Library Generation for Programmable Logic Devices
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Solution Overview
Problem
Existing delay models for programmable logic devices suffer from low accuracy in calculating wiring route delay due to neglect of physical properties, especially as dimensional shrinkage advances, making the calculation of wiring route delay a critical issue.
Innovation Solution
A delay library generation system that calculates delay information based on the arrangement of logic elements, interconnections, and global interconnections, including extraction of parasitic element parameters and crosstalk, to generate a precise delay library for programmable logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a reference table with constant delay values is used for logic elements, then the delay model is simple to implement, but the calculation accuracy of wiring route delay is low
Solution Approach 1:
The patent applies local quality by creating position-dependent delay values for wiring routes. Instead of using a single constant delay value for all wiring routes, the delay value varies based on the specific position of logic elements on the array. This is achieved by calculating delay values for different wire segments based on their locations, thereby improving calculation accuracy while maintaining a relatively simple tabular structure that can be implemented in delay models.
2Quantity of substance
If dimensional shrinkage of LSI is advanced to increase integration density, then more logic elements can be packed, but wiring route delay becomes a larger percentage of overall circuit delay
Solution Approach 1:
The patent applies segmentation by dividing the wiring route delay calculation into multiple segments or sections. Each wire segment between adjacent logic elements is calculated separately with its own delay value based on position. This segmented approach allows the system to accurately capture the increasing significance of wiring delays in high-density designs, where each individual wire segment's delay becomes more critical to the overall circuit performance.
3Productivity
If constant delay values are used for all wiring routes, then the delay model is computationally efficient, but physical properties of wiring routes are not considered
Solution Approach 1:
The patent applies parameter changes by varying the delay parameter based on the position of wiring routes. Instead of using a constant delay value, the delay parameter is changed according to the location of logic elements on the array. Position-dependent delay values are calculated and stored in tables, allowing the system to consider physical properties of wiring routes while maintaining computational efficiency through pre-calculated lookup tables rather than complex real-time calculations.
Data Source
AI summary
A delay library generation apparatus, associated control method, and associated program are provided. The delay library generation apparatus comprises a storage device which stores architecture information of a logic element array, layout data of an overall programmable logic device, a netlist of the overall programmable logic device, and a wiring route extraction unit which refers to the storage device and extracts wiring route information regarding a wiring route section based on the architecture information. Moreover, the delay library generation apparatus comprises an analyzing unit which analyzes the layout data of the logic device and extracts parameters of a parasitic element and a crosstalk between adjacent interconnections. The delay generation apparatus further comprises a delay calculation unit which calculates delay data based on the extracted parameters and a delay library generation unit which generates a delay library of the logic device based on the wiring route information and the delay data.