Delay-Line A/D Conversion for Low-Power Power Supply Sampling
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Solution Overview
Problem
Existing A/D converters for digitally controlled power supply systems are costly, power-intensive, and inefficient, particularly in low-power applications, due to high material costs, silicon area requirements, and power consumption.
Innovation Solution
A delay line-based A/D conversion method that compares a reference signal to a ramp signal, propagates a signal through a delay line, and stores its state when the ramp signal crosses the reference or input signal, allowing for efficient digital conversion with reduced power consumption and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a flash A/D is used in a power supply system, then conversion speed is improved, but area and power consumption become prohibitive
Solution Approach 1:
The flash A/D converter is segmented into multiple stages: a coarse conversion stage using a smaller flash A/D, followed by a fine conversion stage using a delay-line A/D. This segmentation allows the system to achieve high conversion speed through the parallel flash approach while reducing overall power consumption and area by using a more efficient delay-line mechanism for the fine conversion portion.
Solution Approach 2:
The invention transitions from a purely time-domain flash conversion approach to incorporating a delay-line based time-to-digital conversion dimension. By converting the analog voltage to a time interval (via the ramp generator and comparator) and then measuring that time interval through delay elements, the system achieves flash-like speed with reduced power and area requirements.
2Use of energy by stationary object
If a Successive Approximation A/D is used, then power efficiency is improved, but multiple clock cycles are required making it difficult to use with multiplexed input at high per-channel sample rates
Solution Approach 1:
The system performs preliminary coarse conversion using a flash A/D before the fine conversion stage. This preliminary action establishes a starting point for the delay-line based fine conversion, allowing the system to achieve high sample rates without requiring multiple sequential clock cycles for each bit of precision.
Solution Approach 2:
The delay-line A/D converter uses dynamic delay elements that can be selectively activated based on the coarse conversion result. This dynamic approach allows the conversion process to adapt to the input signal characteristics, achieving high speed conversion without the fixed sequential timing constraints of successive approximation converters.
3Adaptability or versatility
If multiple A/D converters are used for multiple power supplies, then conversion capability is improved, but cost, silicon area, and power consumption increase
Solution Approach 1:
The delay-line A/D converter design is implemented as a universal module that can be shared across multiple power supply channels through time-division multiplexing. The converter can be rapidly reconfigured to serve different channels sequentially, providing multi-functionality that reduces the total number of A/D converters needed while maintaining the ability to handle multiple power supplies.
Solution Approach 2:
Multiple A/D conversion functions are merged into a single converter instance by combining the flash A/D coarse conversion stage with the delay-line fine conversion stage in an integrated architecture. This merging allows the system to achieve the functionality of multiple converters with the resources of one, reducing overall power consumption and silicon area.
Data Source
AI summary
In one embodiment, a method of performing an A/D conversion includes comparing a reference signal to a ramp signal, comparing an input signal to the ramp signal and causing a signal to propagate through a delay line when the ramp signal crosses a first of the reference signal or the input signal. The state of the delay line is stored when the ramp signal crosses a second of the reference signal or the input signal after the ramp signal crosses the first of the reference signal or the input signal.


