Self-Calibrating Delay Line Flash ADC for Fast Transient Tracking
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Solution Overview
Problem
Conventional tracking ADCs face limitations in tracking high-speed transients due to large area and power consumption from multiple comparators, and they can only digitize low bandwidth signals, making them unsuitable for applications requiring precise detection of fast slew rates and higher efficiency in power converters.
Innovation Solution
A self-calibrating delay line flash ADC system with integrated calibration circuitry, including a signal generator and delay line ADCs, that uses voltage-to-time conversion and calibration loops to improve accuracy and efficiency, replacing multiple comparators with a single delay line ADC to enhance bandwidth and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple comparators are used in conventional tracking ADC to improve measurement precision, then conversion accuracy is improved, but device area and power consumption increase
Solution Approach 1:
The patent combines multiple comparator functions into a single delay line flash ADC structure. Instead of using separate comparators for each bit of resolution, the invention uses a unified delay line architecture where multiple delay elements work together to achieve the same comparison function, thereby reducing the total device area while maintaining conversion accuracy.
Solution Approach 2:
The patent replaces the traditional mechanical/comparator-based conversion mechanism with a voltage-to-time conversion approach. By converting the analog voltage difference into a time delay signal and then digitizing it, the system eliminates the need for multiple physical comparators, reducing area consumption while preserving measurement precision.
2Measurement precision
If multiple comparators are used in conventional tracking ADC to improve measurement precision, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple comparator operations into a single delay line flash ADC structure. By consolidating the comparison functions into one integrated circuit block rather than using multiple separate comparators, the total power consumption is reduced while the conversion accuracy is maintained through the coordinated operation of delay elements.
Solution Approach 2:
The invention substitutes the power-intensive comparator-based conversion mechanism with a voltage-to-time conversion system. This approach uses less power because it avoids the continuous operation of multiple comparators, instead using a single conversion event that transforms voltage differences into time delays for digitization.
3Device complexity
If conventional tracking ADC is used to digitize low bandwidth signals, then device complexity is reduced, but bandwidth capability is limited
Solution Approach 1:
The patent replaces the traditional sequential comparator-based conversion system with a parallel voltage-to-time conversion architecture. This substitution enables the system to handle high-bandwidth signals because the conversion happens in a single cycle without the sequential limitations of traditional ADCs, while the device complexity remains manageable through the use of standardized delay elements.
Solution Approach 2:
The invention introduces dynamic elements through the delay line architecture, where the propagation delay through each stage can be dynamically adjusted or optimized. This dynamic characteristic allows the system to respond to high-frequency signals effectively, increasing bandwidth capability while maintaining reasonable device complexity through systematic design of the delay stages.
4Speed
If larger error quantizer is used to track faster slew rates, then tracking speed is improved, but device area and power consumption increase
Solution Approach 1:
The patent substitutes the traditional approach of increasing quantizer size to improve tracking speed with a voltage-to-time conversion mechanism. By converting voltage differences into time delays that can be rapidly digitized, the system achieves fast tracking of slew rates without requiring a larger physical quantizer structure, thereby maintaining compact device area.
Data Source
AI summary
An apparatus as discussed herein can be configured to include a delay line analog-to-digital converter operable to convert an analog error voltage into a digital error voltage signal. Additionally, the apparatus can be configured to include an integrator function as well as a digital to analog converter. The integrator function is operable to produce a digital value representative of an analog input voltage, the digital value adjusted based on samples of the digital error voltage signal generated by the delay line analog-to-digital converter. The digital-to-analog converter operative to convert the digital value received from the integrator function into a second analog voltage, the analog error voltage being a difference between the input voltage and the second analog voltage.