Delay Line Circuit Aging Control With Periodic Toggle Signals
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Solution Overview
Problem
Electronic circuits, particularly delay lines, experience asymmetric aging effects due to un-selected delay elements being maintained in a static state, leading to inconsistent output signal rise and fall times, which can affect the timing of other digital circuits.
Innovation Solution
Incorporating delay selection logic and enable logic to select a subset of delay elements for signal delay, while providing a periodic signal to remaining elements to cause them to transition between logic states at a frequency less than the input signal, reducing asymmetric aging effects without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If un-selected delay elements are maintained in a static state to save power, then power consumption is reduced, but asymmetric aging effects occur leading to inconsistent output signal rise and fall times
Solution Approach 1:
The patent applies periodic action by providing periodic toggle signals to un-selected delay elements, causing them to transition between logic states periodically rather than remaining static. This periodic activation prevents asymmetric aging effects while consuming minimal power, as the elements are not continuously active but periodically refreshed to maintain signal consistency.
2Reliability
If all delay elements are kept active to prevent aging, then signal consistency is maintained, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of delay elements based on their selection status. Selected delay elements remain actively processing signals, while un-selected elements receive periodic toggle signals instead of continuous activation. This localized differentiation maintains signal consistency where needed while reducing power consumption in non-critical paths.
Solution Approach 2:
The patent uses periodic action to activate un-selected delay elements only when needed for aging prevention, rather than keeping them continuously active. The periodic toggle signals ensure these elements periodically transition between logic states, preventing asymmetric aging while minimizing power consumption compared to continuous activation.
3Reliability
If delay elements are frequently toggled to prevent aging, then asymmetric aging effects are reduced, but power consumption increases
Solution Approach 1:
The patent applies periodic action by toggling un-selected delay elements at reduced frequencies compared to fully active elements. This periodic activation is sufficient to prevent asymmetric aging effects while consuming significantly less power than continuous high-frequency toggling, achieving a balance between aging resistance and power efficiency.
Solution Approach 2:
The patent applies parameter changes by adjusting the toggle frequency of un-selected delay elements to be lower than that of selected elements. This parameter adjustment maintains aging resistance by ensuring periodic transitions occur, while reducing power consumption through lower frequency operation in non-critical paths.
Data Source
AI summary
A delay line can include a number of delay elements connected in series, each selected to impart an overall delay to an input signal. The delay line can include delay selection logic to select a subset of the delay elements to delay the input signal. The delay line can include delay element enable logic to enable the selected subset of the delay elements to delay the input signal. Further, the remaining delay elements can be disabled from contributing any delay to the input signal, and a respective periodic signal can be provided to at least one of the remaining delay elements to cause the at least one remaining delay elements to output an output signal that is a function of the respective periodic signal and that has a frequency less than that of the input signal. This configuration can reduce asymmetric aging effects on the delay line.